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8254/82C54 Programmable Interval Timer
 
Technical questions and answers

Q1. What is it?
A1. The 82C54 is a counter/timer device designed to solve the common timing control problems in microcomputer system design. It has three independent 16-bit counters, each capable of handling clock inputs up to 10MHz. The device has six programmable timer modes which allow it to be used as an event counter, an elapsed time indicator, a programmable one-shot, and many other applications.

Q2. Is the 8254-2 backwards compatible to the 8253? What is the relationship between the 8253/8254/82C54?
A2. The pin-out is the same but the 8254/82C54 is a superset of the 8253, not a "fix" of the 8253. The 8254 is a completely new design with several added features including Read Back Command and 10MHz CLK input (8254-2 and 82C54-2). The software is not exactly the same as that used with the 8253. The 8254 does fix the 8253 Mode 3 "count of 3" bug. Details can be found in the 8254 data sheet Mode 3 description.

Q3. Are there application notes?
A3. There are no Intel Ap-Notes available but a document titled "8254/82C54: Introduction to Programmable Interval Timer" exists on the World Wide Web; A 7-page document describing the operation of the device.

Q4: Is there any errata for the device?
A4. There is very important errata:

(1) "82C54 TWC/TCL Errata and Tech Bit" dated 5/19/94. This errata applies only to the CHMOS version of the device. Failure to implement corrections for the errata may result in infrequent but devastating customer system/application failures.

(2) "82C54 Programmable Interval Timer Mode 0 Errata" dated 5/23/94. This errata applies only to the CHMOS version of the device.

Q5. What does "NOTE: A GATE transition should not occur one clock prior to terminal count" mean?
A5. Modes 2 and 3 use the clock frequency for the RATE Generator and Square Wave Mode respectively. In modes 2 and 3, the 8254 (and 82C54) uses "look ahead" logic to precondition OUT to go low on the falling edge of the CLK input upon terminal count. Without this look ahead feature, the 8254 would not have time to resolve its internal logic at the same time OUT is to go low upon reaching terminal count. Monitoring the count value in software, before disabling counting via the GATE, is usually sufficient to prevent this combination of events. This has always been the operation of the 8254 (and 8253, and 82C54) and no problems resulting from this have been reported.

Q6. What is the meaning of "In Modes 2 and 3, if a CLK source other than the system clock is used, GATE should be pulsed immediately following WR# of a new count value?"
A6. The GATE input, when low in MODE 2, will force the output high. When the GATE input goes high, the counter will start from the initial count. The GATE can be used to synchronize the counter. In MODE 3, the output will remain high until 1/2 the count has been completed and go low for the other half. In both cases the CLK input is used as the pulse period. If the system clock is not the 8253 CLK input, you must pulse GATE following WR# of a new count value to synchronize the loading of the new count.

Q7. What is the default state of the 8254 upon power up or reset?
A7. The device does not have a dedicated reset pin. At power up, the default condition of the 8254 is undefined. The mode, count value, and state of the OUT pins are undefined or random. Each counter must be initialized via software before it can be used.

Q8. Can the CLK be used to start and stop counting?
A8. No. This can cause the counter to lock up and require reprogramming the 8254 before further operation is possible. Turning the CLK on or off usually results in noise spikes. These spikes appear to the 8254 as CLK input pulses which violate TPWH and TPWL timing. The internal counter logic is unable to resolve the high or low state of the CLK input and locks up.

Q9. In Mode 2, when the counter is programmed with a count of 1, why does OUT remain high and never go low?
A9. This is due to the internal look ahead logic, as described in question 5, above, and the reloading of the count in Mode 2. As described in the data sheet, the count is loaded from the CR to the CE on the falling edge of the CLK input. One CLK input pulse prior to terminal count, the 8254 internal look ahead logic conditions OUT to go low on the falling edge of the next CLK input pulse. The terminal count CLK input pulse falling edge should cause the OUT to go low immediately but is overridden by the CR to CE count reload occurring on the same CLK input falling edge. This conflict results in OUT remaining high continuously. Also, a count of 1 in Mode 2 is not appropriate (or useful). A count of 1 in Mode 2, Rate Generator Mode, would result in a rate of 1. In theory, this would be a square wave with a period the same as the CLK input. Should the user require such an output, Mode 3, Square Wave Mode, is the appropriate choice.

Q10. How to read the original value programmed into the counter?
A10. This is unsupported. The Count register (low and high) cannot be read. The Output Latch (low and high) are the only things which can be read. In other words, only the value of a counter can be read, not the initial count programmed into the device.

Q11. With one of the counter's GATE pin tied high in Mode 2, is there a way to have the OUT signal low for an indefinite period of time without any hardware modes. Can this be done by loading a value of 1 and keeping the OUT low?
A11. It appears there is no way to do this in Mode 2 without external logic like a PAL. There are other Modes where once a count is occurring when OUT is low, a GATE low will cause the count to remain at the same number keeping OUT low until the GATE goes high again.

Q12. How to set up an outer-inner loop? For example, have counter 2 decrements and use its OUT transition to triggers counter 1 to start counting? Counter 1 must stop after one count until the next transition of the counter 2 OUT pin.
A12. First of all, a count of one in mode 2 is illegal. Next, in counter 2 OUT will initially be high. When counter 2 decrements to 1, OUT goes low for one clock pulse. Counter 2 OUT then goes high again, counter 2 reloads the initial count, and the process is repeated. The OUT transition from counter 2 (high-->low for one clock pulse-->high) can trigger counter 1 to start its count. This will occur on the rising edge of the counter 2 OUT pulse if the counter 2 OUT signal is tied to the counter 1 GATE input. Counter 1 will start to decrement its count. (Counter 2 already reloaded its count and is also counting down.) Counter 1 OUT is high. When counter 1 reaches 1 the counter 1 OUT goes low for one clock pulse. Counter 1 OUT then goes high again, counter 1 reloads the initial count, and the process is repeated. The OUT transition from counter 1 can be used to do something in the system. Meanwhile, counter 2 is still counting down, as is counter 1. When counter 2 decrements to 1 there will be an OUT transition from counter 2 to the counter 1 GATE input. This GATE transition at counter 1 (which is also still counting) disables the counter 1 count, then re-enables it. The solution appears to be to invert the OUT signal from counter 2 so that it is always low until the counter 2 decrements to 1. At that time it will go high triggering counter 1 for one pulse. Counter 1 will only decrement at the point in time when counter 2 reaches 1, pulses OUT, and reloads to start again. Counter 1 never reloads and never pulses the counter 1 OUT signal until counter 1 gets down to 1. This whole scenario sounds complicated. Why not use mode 3 in counter 2 and mode 2 in counter 1?

Q13. Were there any additional features added to the "-2" version? Did this part fix the timing errata found in the plain 82C54 part?
A13. The 82C54-2 was just a result of the 1993 Inventory Reduction Program. We limited the variety of many parts to just the highest speed. The 82C54-2 is the 10MHz device and it is the only one available now. There were no changes to the device itself and the errata still exists.

Q14. Is it possible to replace the counter value "on the fly" ? What is the impact of this?
A14. The count will continue until the new number is written completely into the Count register. Both bytes are transferred to the CE simultaneously.

Q15. What exactly do the TWC min and max timing requirements mean?
A15. TWC: CLK delay for loading. The TWC specification defines the relationship between the writing of a control word or count value and the CLK pulse. The parameter TWC defines whether the results of the write operation will (TWCmin) or will not (TWCmax) be reflected in the subsequent device operation following the CLK pulse. Please see the TWC errata described in Q4 above.

Q16. Does CS# need to be held active after RD# is removed?
A16. The data sheet pictures of the write/read timing cycles are confusing. They show that as RD# reaches the high state of 2.0V (inactive), CS# can leave the active state (<=0.8V) and start to go high (inactive). This leads to considerations of rise times and indeterminate device states between the high and low signal values. In actual use, CS# does not need to be held active for any time period after RD# is removed.

Q17. Will WR# going active 5-10nS before CS# goes active cause any problems?
A17. 5-10nS should not cause an application problem. Note that timing diagrams referencing the WR# falling edge will now happen on the CS# falling edge or relative to it.

Q18. What is meant by the "clock source"?
A18. The clock source is the input to the CLKx pins on the device. This input should be a derivative of the system clock in 82C54 applications. (See the TWC errata.) The clock source is usually synchronous to the system clock.

Q19. Can different clocks be used with the different timers in the device?
A19. Yes. The three counters are all independent of each other.

Q20. What can cause the counter on the 8254 to occasionally lock up?
A20. There are two possible reasons:

(1) Violations of the TPWH and/or TPWL specifications. See note 3 of A.C. Characteristics in the data sheet for those symbols.

(2) Violations of TR and/or TF specifications., In both cases the device is unable to resolve the state of the CLK input.

Q21. What is the OUT rise time requirement?
A21. The OUT rise time is not specified. Ideally, it is an impulse function and should look as sharp as a clock signal rising edge. There is a spec for the time period between GATE low and OUT high. That time period is 100ns for the -2 device.

Q22. Why is TWC specified to the rising edge of the clock? The clock(s) are loaded on the falling edge.
A22. This is used for software synchronization of loading a new count. The new value must be within the TWC window to guarantee that the new count is loaded on the next falling edge.

Q23. Why should GATE be pulsed immediately following WR# of a new count value when using clock source in modes 2 & 3?
A23. If an asynchronous CLK input is used for a counter, the GATE is used to synchronize the loading of the new count.

Q24. Is it possible to disable counting prior to the terminal count?
A24. In mode 0, 2, 3, and 4, the GATE signal can be used to disable counting prior to terminal count. In these modes, counting is enabled when GATE=1 and disabled when GATE=0. In modes 1 and 5, the GATE input is a Trigger pulse to start the counting sequence therefore it can be used as in modes 0, 2, 3, and 4.

Q25. If counting is disabled prior to terminal count in modes 0, 2, 3, 4, is it possible to restart counting from where it left off?
A25. Yes. In modes 0, 2, 3, 4, counting is enabled when GATE=1 and disabled when GATE=0.,,26. Can the counter/timer be turned off when using the load command?, A26., The counter will not stop decrementing.

Q26. Can the counter/timer be turned off when using the load command?
A26. The counter will not stop decrementing.

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