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82355 Bus Master Interface Controller (BMIC) Overview
 

1.The BMIC does everything it can to perserve EISA bus bandwidth. During EISA writes, it will not take control of the bus until the FIFO is full (or has all of hte data). During EISA reads, the BMIC will not take control of the bus until the FIFO is empty.

2.The IDOE# and IDDIR signals are not driven active during I/O cyccles to the IOSEL# address ranges- as long as these signals are not mapped into the BMIC register space.

3.The Semaphore Ports and the Mailbox registers are designed to allow the board manufacturer to differentiate their design by setting up software based semaphores and message passing. They are general purpose registers.

4.The Doorbell registers are similar to the Mailbox registers except that the Doorbell registers generate interrupts when it is written /programmed. The Doorbell registers generate LINT or EINT to the Local CPU or to the EISA bus.

5.Whenever Channel 0 and Channel 1 have any obstacles (page breaks, aborts, stalls,...) the BMIC will always re-arbitrate the channel transfers. This means that if both channels are loaded, the BMIC will alternate which channel is transmitting after reaching an obstacle.

6.The TEOP# signal is output only.

7.The Transfer Buffer Interface (TBI) transfer data in a DMA type format- moving blocks of data at a time.

8.The TBI will overread up to 28 bytes into the internal FIFO. These "overread bytes" will be flushed from the FIFO when TEOP# is asserted. If both channels are going to be used, care should be taken to prevent the BMIC from overreading valid information for the next transfer.

9.During EISA reads, if the internal FIFO fills up (resulting in a stall) the EISA interface will release the bus by de-asserting MSBURST#. The EISA bus will NOT be relinquish if MREQ# stays active. The BMIC will not start another cycle until the FIFO is empty.

10.EISA Read: Pause (FIFO Empty)

a) EISA Bus will stay active
b)TRQ# goes inactive
c) Next EISA data strobed will strobe data from latches into the FIFO and this will clear the FIFO Empty Flag
d)TRQ# will then go inactive

11.EISA Read: Stall (FIFO Full)

a) EISA Bus is released
b)TRQ# stays active until the FIFO is completely empty
c) TRQ# goes inactive
d) Control transfers to pending channel

12.During EISA writes, whenever the FIFO is emptied (resulting in a stall), the EISA interface will "release" the bus by deasserting MSBURST#. But the EISA bus is not relinquished if MREQ# stays active. The BMIC will not start another cycle (assert START#) until the FIFO is full again.

13.EISA Write- Pause (FIFO Full)

a) TRQ# goes inactive
b) When data is strobed onto the EISA bus until the FIFO is empty
c) TRQ# goes active

14.EISA Write- Stall (FIFO Empty)

a) The EISA bus will be released but MREQ# will stay active
b) On the next active TACK#, control of hte bus will be transferred to the other channel
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