21153 PCI-to-PCI Bridge Datasheet
Intel's 21153 is a second-generation PCI-to-PCI bridge and is fully compliant with PCI Local Bus
Specification. The 21153 has a 64-bit primary bus interface and a 32-bit secondary bus interface. The
64-bit interface interoperates transparently with either 64-bit or 32-bit devices. The 21153 optimizes
the performance of the downstream 32-bit devices on the 64-bit PCI bus. The 21153 provides full
support for delayed transactions, which enables the buffering of memory read, I/O, and configuration
transactions. The 21153 has separate posted write, read data, and delayed transaction queues that
provide significantly more buffering capability than first-generation bridge products. In addition, the
21153 supports buffering of simultaneous multiple posted write and delayed transactions in both
directions. Among the new features provided by the 21153 are: a programmable 2-level secondary
bus arbiter, an IEEE standard 1149.1 JTAG interface, live insertion support, a 4-pin general-purpose
I/O interface, individual secondary clock disables, and enhanced address decoding. The 21153 has
sufficient clock and arbitration pins to support nine PCI bus master devices directly on its secondary
interface.
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