Chief Performance Architect & Senior Principal Engineer
Digital Enterprise Group
Architecture and Planning
Fayé Briggs is the Chief Performance Architect of Digital Enterprise Group, where he helps to drive architectural features into the platform roadmap that will enable delivery of best-in-class performance. He provided leadership for multiple generations of innovative multiprocessor server chipset designs, including current and next generation Xeon DP & MP server chipsets & platform architecture. He conceptualized the 870 scalable(2P-16P) architecture family of server chipsets and led its development.
Prior to joining Intel in 1997, he was a co-architect of Sun's original SPARC processor, contributing to the MP features, memory ordering and coherence. While at Sun, he led the architecture of Sun's first scalable multiprocessor (SunDragon). He was a co-founder and CTO of Axil Computers, where he led the development of over 30 products for servers, storage & workstations, including chipsets, boards & systems.
Fayé has published over 45 technical papers on processor & MP architectures, memory ordering, cache coherence, and performance. He is the co-author of a best seller & pioneering textbook, Computer Architecture and Parallel Processing, published by McGraw-Hill and translated into Chinese & Spanish.
Fayé was a Shell-BP scholar and earned his Bachelor of Engineering in Electrical Engineering with First Class Honors from Ahmadu Bello University, in Nigeria; a Master of Science in EE from Stanford University, and a PhD in Electrical & Computer Engineering from the University of Illinois, Urbana-Champaign. He was a tenured Associate Professor at Rice University and a faculty member of ECE at Purdue University. While in academia, he was a consultant to Exxon, IBM, Motorola and Texas Instruments on characterization of mainframe multiprocessor coherence and cache/TLB designs, respectively. He was appointed by the National Science Foundation as member of a national team to evaluate and deliver a report on Japan's Fifth Generation research and was a Distinguished Visitor of the NSF.
Terrance (Terry) J. Dishongh, Ph. D. is currently the senior principle engineer and lead technologist in Intel's Digital Health Research and Innovation Group. His current duties at Intel Corporation include projections of technology trends in ubiquitous computing, research and development of sensors for healthcare applications, contextual awareness and design of new radio technology for ubiquitous computing. He has design, developed and prototyped various sensors and sensor network using, Z-wave, Zigbee, X10, mote based systems and Bluetooth technology. Previously, Dr. Dishongh was a Staff Architect in System Manufacturing designing and developing the interface between the processor and the chipset for the PentiumT III and 4 systems. His designs for packaging are in the Lakeport Chipset, the Pentium® III Processor (Copper-mine), and the Mobile Pentium® II. In his ten years at Intel he has been awarded the Intel Achievement Award, two TMG Excellence award, six Intel Corporation Divisional Recognition Awards, two achievement awards, over 190 trade secrets, and filed over seventy patents during his tenure at Intel Corporation.
Dr. Dishongh has held faculty positions at the University of Maryland, College Park, and the State University of New York at Buffalo. He has chaired the National Electronic Manufacturers Institution's roadmap for desktop computer systems for the past five years and for four years he authored the NEMI Healthcare sector roadmap. Terry received his Ph.D. in 1996 from the University of Arizona. He received his Master's Degree and Bachelor's Degree from the University Tennessee, Knoxville in 1992 and 1990 respectively. Terry has co-author one textbook and over fifty other publications in electronic packaging, biomedical engineering and structural mechanics. Before his academic career Terry, at the age of 17, was a US Army Green Beret
in the 7th
Special Forces Group Airborne as a volunteer service man. Terry was born in Port Hueneme, California in 1964 and was raised in Pasadena, Texas. Terry currently lives in County Kildare, Ireland with his wife of 22 years, Pamela and his children Katherine (10 years old) and Isaac (8 years old).
Niall Mac Gearailt is a researcher in residence for Fab/Sort Manufacturing (FSM) Research. Niall is responsible for conducting advanced research and development in PCS (Process Control Systems) with a particular emphasis on the areas of metrology reduction and equipment performance improvement. He is also responsible for establishing and leading collaboration programs between Intel and universities to address key technology problems. His charter includes harvesting viable research results and demonstrating business value in the Manufacturing environment.
Niall joined Intel in 2002 as a process engineer and worked developing fault detection systems using advanced sensors before moving into his research role in 2005. Before that he was 8 years with Lam Research where he worked as an R&D engineer developing next generation plasma chambers and processes. He also spent a number of years at various wafer fabrication facilities in San Jose, California.
Niall received a bachelor's degree in Mechanical engineering from University College Dublin in 1991 and is currently completing his PhD at Dublin City University.
Principal Engineer and Director of Technology Development,
Technology and Manufacturing Engineering,
Paula Goldschmidt graduated from the Hebrew University with a B.Sc. (1977) in Chemistry and Physics and M.Sc. degree (1980) in Applied Chemistry. She joined Intel as a Process Engineer in 1983 and since then held numerous management positions within Fab8. Over the last few years, Paula leads Technology Business Development teams in FSM, managing Technologies Gap Closure collaborations with suppliers and potential suppliers for Intel, reporting into TME. In this job Paula created a unique new concept of business development - EMEA focused - utilizing existing Intel Corp resources in the VF and TD sites. The team supports more than 50 active projects in parallel, in cooperation with FSM engineers. Through this operation, many Israeli and European manufactured tools were selected for Intel future technologies.
Mike Goldstein is a Principal Engineer in General Fab Materials organization at Intel Corp. In his current position, Mike is directing the material development activities for metal interconnects and supporting the silicon pathfinding activities.
Mike joined Intel 22 years ago as a Material Scientist in charge of silicon material development and continued to be involved through the years in the silicon transitions from 4" wafers to 300mm wafers (being currently involved on 450mm wafers development).
During his career at Intel, Mike supported and managed, in addition to silicon a diverse range of materials development activities including interconnects, C4, CMP...
Mike published more than 50 patents and papers covering different aspects of IC manufacturing.
Mike is also supporting industry wide activities, co-chairing the ITRS Starting Material Working Group and ISMI 450 mm Starting Material Focus Team and chairing the SEMI standards committee preparing the "450mm Mechanical Test Wafer" specification.
Mike holds a PhD in Chemistry from Ben-Gurion University in Beer Sheva, Israel, a Masters in Material Science and a Bachelor degree in Physics and Math from the Hebrew University in Jerusalem, Israel.
Founding Director of the Intel Barcelona Research Centre
Antonio González received his M.S. and Ph.D. degrees from the Universitat Politècnica de Catalunya (UPC), in Barcelona, Spain. He is the founding director of the Intel Barcelona Research Center, whose research focuses on new microarchitecture paradigms and code generation techniques for future microprocessors. Prior to his career at Intel, he joined the faculty of the Computer Architecture Department of UPC in 1986 and became a Full Professor in 2002. He currently holds a part-time Professor position at this department.
His research has focused on computer architecture, compilers and parallel processing, with a special emphasis on processor microarchitecture and code generation. He has published over 180 papers, has given over 60 invited talks and has filed 10 patents in the areas of Power-Aware Microarchitectures, Clustered Microarchitectures, Speculative Multithreaded Processors, Data Value and Data Dependence Speculation and Reuse, Cache Architectures, Register File Architecture, Modulo Scheduling, Code Analysis and Optimization, Parallel Algorithms, Prolog-Oriented Architectures, Instruction Fetching Mechanisms, and Digital Image Processing.
Dr. González is an Associate Editor of the IEEE Transactions on Computers, IEEE Transactions on Parallel and Distributed Systems, ACM Transactions on Architecture and Code Optimization, and Journal of Embedded Computing. He has served on over 50 program committees for international symposia in the field of computer architecture, including ISCA, MICRO, HPCA, PACT, ICS, ICCD, ISPASS, CASES and IPDPS. He has been program (co-) chair for ICS 2003, ISPASS 2003 and MICRO 2004, among other symposia.
Director Higher Education & Research
European Union Region
Prof. Mark Harris was born in Marion-Iowa, USA on November 25th
After completing Elementary, Junior and High School, moved to Europe to study Computer Science (Informatik) and Economics (Wirtschaftswissenschaften) at the Technical University of Munich.
Prof. Harris joined Intel in 1983 holding a number of Engineering, managerial and Director positions before 2003 assuming responsibility as Director of Higher Education & Research for the European Union Region; responsible for advancing innovation in key areas of Intel, collaborating with top universities in the European Union to expand university curricula, engage in focused research, and encourage students to pursue a range of opportunities for technical study and research. The Intel® Higher Education & Research Programs are successfully running in over 70 Universities in 19 EU member states. Prof. Harris is also Worldwide Program responsible for the Intel® Technology Entrepreneurship Program - Theory to Practice, a Program in Partnership with UC Berkeley's Haas School of Business.
Prof. Harris holds Master Degrees in Computer Science and in Economics from the Technical University in Munich and also holds Professorships as Associated Professor for Technology Entrepreneurship at the University Politehnica of Bucharest as well as Associated Professor for Entrepreneurship in IT at the University of Sofia.
In May 2007 Prof. Harris was awarded with a Doctor honoris causa from the University of Sofia, Faculty of Mathematics and Informatics.
Prof. Harris is married and has 2 young children (8,4).
Ministry of Education and Culture
Born on May 7, 1964 in Sopron. He graduated from the Humanities Faculty of Eötvös Loránd University majoring in History and Latin in 1988. Subsequently he began working at the Department of the Mediaeval and Early Modern History of Hungary. In 1990 he obtained his university doctorate and in 1996 he earned his PhD. From 2001 he has been an associate professor at the university.
In 1989 he was one of the founders of the Hungarian Socialist Party (MSZP). Between 1998 and 2000 he was the deputy chairman of the national presidium and since 2000 he has been a member of the board of the national presidium. In 2002 he became the deputy president of the Party and in 2004 he was elected as Party President.
He has represented Pesterzsébet-Soroksár (Budapest constituency no.29.) as an individual representative since 2002. Between 2002 and 2003 he was the political secretary of state of the Ministry of Education and subsequently from 2003 through 2005 he was the Minister of Culture.
He is married with two sons. His wife, Julianna Farkas is an associate college professor.
Intel Senior Fellow, Corporate Technology Group
Director, Communications Technology Lab
Dr. Kevin Kahn is an Intel Senior Fellow and Director of the Communications Technology Lab, a corporate advanced development and research lab in Intel's Corporate Technology Group responsible for all communications technologies including radio, optical, and copper physical layer technologies, CMOS communications circuits work, packet processing, and higher layer protocols. Additionally, he helps drive communications strategies and policy for the corporation. Some of his primary current focus areas are broadband access to the home, wireless LANs and PANs, spectrum policy, and related Internet issues.
Dr. Kahn also coordinates Intel RF technical directions across divisions and chairs the Intel Communications Research Council, which oversees research activities between Intel and academic programs. He currently serves on the FCC Technological Advisory Council, the Computer Science and Telecommunications Board of the National Research Council, and on various academic advisory committees.
In prior lab assignments, Dr. Kahn has played a variety of roles in strategic and technical planning and research. These included managing large labs in operating systems and Internet communications.
Dr. Kahn represents Intel in various industry consortia and various government policy forums. He has lectured widely at universities in the U.S. and abroad about Intel and personal research activities. He previously served on the National Academy of Science Broadband Last Mile Study Panel, served as the co-chair of the Universal ADSL Working Group, an industry alliance dedicated to accelerating the deployment of consumer ADSL services for higher speed Internet access, and served as a Director of the DSL Forum.
Dr. Kahn joined Intel in 1976 after completing a Ph.D. in Computer Science at Purdue University. Prior to that, he had received an M.S. in Computer Science from Purdue and a B.S. in Mathematics from Manhattan College. Throughout his 27-year career with Intel, he has worked in system software development, operating systems, processor architecture, and various strategic planning roles. He has held both management and senior individual contributor roles. He holds multiple patents in processor architecture and communications technologies.
Dr. Kahn is based at Intel's facility in Hillsboro, Oregon.
Ministry of Economy and Transport
Born on July 5, 1972 in Budapest. Graduated from the Faculty of General Medicine of Semmelweis University of Medical Sciences in 1996.
Between 1996 and 2004 he was the CEO of Elender Computer Ltd. (Elender Computer Kft.), and CEO of the legal successors of the company. Between 1999 and 2001 he was also the European deputy president of PSINet Inc. He has been president of the Association of Information Technology Enterprises since 2003 and chairman of the Information Technology Program of the Committee of the Office for National Research, Development and Technology since 2004.
He has been Minister of Economy and Transport since 2004. He was elected to Parliament in 2006.
He is married with one daughter.
Intel Assignee at IMEC
Scott List is currently on assignment with Intel as the Strategic Director of Interconnect Research at IMEC in Belgium. From 1999-2004, Scott was the manager of Advanced Interconnect Solutions in the Components Research Department at Intel working on 3D wafer stacking, high frequency measurements, decoupling capacitors and advanced packaging solutions. He also served as the chairman for Intel's process/design/packaging 45 nm silicon technology roadmap and represented Intel at the SRC backend process technical advisory board. From 1990 to 1999, Scott was at Texas Instruments working on the integration of xerogel low k dielectrics, advanced transistor design and characterizing the effects of defects in HgCdTe infrared photodetectors. Scott worked on high temperature superconductors as a post doc at Los Alamos National Laboratory, received his PhD from Stanford's Applied Physics department and his BS from Cornell's Engineering Physics program.
Intel Fellow, Technology and Manufacturing Group
Director, Logic Technology
Quality and Reliability
Jose Maiz is an Intel Fellow and director of Logic Technology Quality and Reliability. He joined Intel in 1983, and was promoted to fellow in 2002. He is presently responsible for identification of silicon reliability limiters to scaling, and their resolution for Intel's next generation silicon technologies and logic products.He first joined Intel's 1Mbit DRAM program transitioning to the 1µm logic technology generation. He has since led silicon reliability teams at various phases of development, including the ramp readiness of the 180nm technology generation. Since the mid 80's, he has been a major force in integrating technology reliability with technology development to ensure that Intel's logic processes are robust for reliability while delivering top performance. He has originated or developed many innovative Quality and Reliability methodologies, including Electromigration under non-direct currents and on short lines, use of SCRs and specially designed transistors for Electrostatic Damage protection, risk assessment methodologies, use conditions to assess reliability risk, improvement of electromigration capabilities for copper, and inter-leaving rules to protect memories against soft errors, among others. He is presently focused on the 45nm technology. Maiz holds 4 patents and has 10 more pending. He has authored or co-authored over 25 publications and conference presentations, a number of them invited. He is presently co-editor of a special issue of IEEE Transactions in Device and Materials Reliability focused on soft errors.
He is a co-recipient of an Intel Achievement award for the "Development of a complete solution for ESD protection on logic technologies using standard cells" in 1991 and has received numerous divisional recognition awards. He is also a Fulbright Scholar (1978). Jose Maiz was born in San Sebastian, Spain, in 1954. He graduated with a degree in physics from the University of Navarra in San Sebastian in 1976. He then moved to the U.S., graduating with a master of science and a Ph.D in Electrical Engineering from Ohio State University in 1980 and 1983 respectively.
Intel Senior Fellow, Technology and Manufacturing Group
Director, Manufacturing Strategic Support
Eugene S. Meieran, Intel Senior Fellow, transferred to Intel Research in CTG in 2007 after spending 34 years in TMG. He is working on introducing advanced innovation and collaboration technology into Intel to help improve internal overall business performance.
Meieran joined Intel Corporation in 1973 as manager of package development (now ATD), with responsibility for developing new lines of device packages for the emerging memory and microprocessor product lines. In 1977 he transferred to the Quality and Reliability Department, responsible for Intel incoming materials quality, creating the new Materials Analysis Laboratories and for key elements of the manufacturing quality and reliability functions. In 1985, he was appointed as Intel Fellow, the second in the company's history. In 2007, he transferred from TMG to CTG.
He is currently a member of the Intel Research Council and the Intel Academic Relations Council, and was Intel's representative to the Semiconductor Research Corp. (SRC) Factory Sciences Board. He has received two Intel Achievement Awards.
Meieran received his bachelor's degree from Purdue University in 1959 and his master's and ScD degrees from the Massachusetts Institute of Technology, Cambridge, Mass. in 1961 and 1963, respectively, in the field of Material Science.
Principal Engineer and Materials Technology & Engineering Manager
Mansour Moinpour, Ph.D., is Principal Engineer and Materials Technology & Engineering Manager at Intel's Materials Organization. His current focus is directing development activities for CMP, Back End dielectrics and interconnects materials (including Low K materials), and supporting path finding and research activities in various novel materials such as polymers, nano particles, etc.. Prior to that his work focused on equipment selection and improvements for Thin Films and Diffusion Modules in Fab Capital Equipment Development (FCED) organization. From 1994-1997, Dr. Moinpour worked at Intel's California Technology and Manufacturing (CTM/D2) where he was responsible for process and technology development in CMP, CVD and metallization areas for advanced deep sub-micron Logic and Flash memory devices. He received his Ph.D. in Materials Science and Engineering from the University of Washington, Seattle, WA. Before joining Intel in 1991, he served as a research assistant professor and lecturer at the Department of Electrical Engineering and the Department of Materials Science and Engineering at the University of Washington. He has served in the faculty advisory committee of the Department of Materials Science & Engineering, University of Washington from 1995-present. He is also an affiliate member of advisory committee of the Department of Mechanical Engineering at Tufts University in Boston, MA. He has authored and/or co-authored over 120 technical papers, presentations and invited talks. He holds 10 patents w/ several more pending.
Vice President, Sales and Marketing Group
General Manager, Europe, Middle East, Africa
Christian Morales is vice president of the Sales and Marketing Group and general manager of Intel Europe, Middle East and Africa (EMEA). He is responsible for Intel® product sales and marketing in the EMEA region.
Morales has held various senior international management roles in sales, channel operations and general management. He brings extensive experience in marketing and building brand awareness for new product segments, as well as a very strong background in expanding and driving Intel's business into new and emerging markets.
Prior to this role, Morales was Intel's vice president of the Sales and Marketing Group and co-general manager of Asia Pacific responsible for implementing Intel's strategies in Asia. He was also responsible for championing Intel's worldwide emerging market strategy.
Before that, he was general manager of Latin America and was instrumental in helping to establish a new regional headquarters and expand the company's regional presence throughout the continent. He joined the company in 1980 in Paris as an Intel field sales engineer and in 1983 became director for Spain and Portugal, and then moved back to Paris in senior positions to manage Western Europe channels and OEMs.
He has been based in Paris, Madrid, Sao Paulo and Hong Kong.
Morales graduated with an electrical engineering degree from the Electricity, Mechanics and Electronics Engineering School in Paris. In 1990, he completed the Young Managers Program in the MBA program at Insead.
Noel Murphy started with Digital Equipment Corp in 1988 working as a test engineer, initially on power supply ICs, and later on disk drive designs. He started his design career working on read channel designs for disk drives. He later worked with Tellabs on the design of communication chips. Noel started up the Silicon Design Team in Shannon for Basis Semiconductor in 2000 which was acquired by Intel later that year. He has worked on the IXP product lines leading the IXP23xx product development. Noel's interest is in low power logic design especially in embedded environments.
Noel earned his Bachelors of Electronic Engineering in University College Cork in 1988 and followed up with a Masters of Engineering from the University of Limerick in 1993. Noel is chair of MIDAS Ireland (Microelectronic Industry Design Association) which is a joint industry and academic cluster defining the future direction of Integrated Circuit design in Ireland.
Intel Senior Fellow
Digital Enterprise Group
Chief Technology Officer, Digital Enterprise Group and
General Manager, Architecture and Planning
Stephen S. Pawlowski is an Intel Senior Fellow. He is the Digital Enterprise Group chief technology officer and general manager for Architecture and Planning for Intel Corporation.
Pawlowski joined Intel in 1982. He led the design of the first Multibus I Single Board Computer based on the 386 processor. He was a lead architect and designer for Intel's early desktop PC and high performance server products and was the co-architect for Intel's first P6 based server chipsets. He helped define the system bus interfaces for Intel's P6 family processors, the Pentium® 4 processor and ItaniumT processor. He also created and led the research for Intel's agile radio architecture for a future generation of wireless products and prior to his current assignment was the director of Corporate Technology Group's Microprocessor Technology Lab.
Pawlowski graduated from the Oregon Institute of Technology in 1982 with bachelor's degrees in electrical engineering technology and computer systems engineering technology, and received a master's degree in computer science and engineering from the Oregon Graduate Institute in 1993.
Pawlowski holds 56 patents in the area of system, and microprocessor technologies. He has received three Intel Achievement Awards.
Director, Fab Sort Manufacturing Research
Gopal is the Director of Fab/Sort Manufacturing (FSM) Research. He is responsible for a research thrust in FSM aimed at addressing key high volume manufacturing issues and developing a FSM/Academic research relationships. In this role, Gopal chairs the technical and management committees to identify key research thrusts in Manufacturing, evaluate research projects, provide funding and help facilitate the implementation of viable research results into manufacturing. Gopal is active in several organizations/consortia. Specifically, he is one of the Intel representatives to the Stanford University’s Alliance for Innovative Manufacturing (AIM), he is also a co-chair of Factory Operations team of the ITRS and a board member of the University of New Mexico’s Anderson School of Management. Gopal has lectured on Manufacturing at Stanford University at other institutions.
Gopal Rao has been working in Intel for the past 18 years. He previous jobs were at Philips Research Labs, Eindhoven and Texas Instruments, Dallas. During his long tenure at Intel, Gopal has held various Engineering and Management positions in process technology development, process integration, process/product qualifications and Quality and Reliability. His experience at Intel has been very broad and has spanned the entire spectrum from suppliers to customers. Gopal holds two Masters Degrees in Physics and Solid State Materials from Birla Institute of Science & Technology (India) and Indian Institute of Technology (India) respectively.
In addition to various paper publications, Gopal Rao is the author/co-author/editor of the following books: "Multilevel Interconnect Technology"
by Gopal Rao, McGraw Hill & Intel 1993, “Guidebook for Managing Silicon Chip Reliability”
by Michael G. Pecht
*, Riko Radjojcic
*, Gopal Rao
*, CRC Press, December 1998, “Microelectronic Manufacturing Yield, Reliability and Failure Analysis”
25-26 October 1995, Austin, Texas (Proceedings of SPIE – The International Society for Optical Engineering, V. 2635.) by Gopal K. Rao
* (Editor), Massimo Piccoli
* (Editor), Society of Photo-Optical Instrumentation Engineers.
Director, Microarchitecture Research
Intel Israel Development Center
Ronny Ronen is the director of the Microarchitecture Research in the Intel Israel Development Center in Haifa. The research group focuses on promoting microarchitecture innovations to improve performance and reduce power consumption of future Intel IA32 processor generations. Ronny was heavily involved in the definition stages of the Intel Pentium M processor and its successors. Past research in the group focused on microarchitecture innovations for high performance - including topics like ILP improvements, enhanced instruction caching structures, and more.
Prior to his microarchitecture activities, Ronny led the Pentium® Processor compiler and performance simulation activities in the Intel Israel Software department (in Haifa). Before that he was involved in various software projects, most notably the development of software development tools for the 8051 microcontroller, leading the hosting of Intel tools on the VAX/VMS environment, leading the iRMX-286 R2.0 OS development, and leading the development of i860 software development tools.
Ronny received his B.Sc. and M.Sc. degrees in Computer Science from the Technion, Israel Institute of Technology, in 1978 and 1979 respectively. Ronny holds over 20 patents and has published 15 papers. Ronny is an Intel Senior Principal Engineer and a Senior Member of the IEEE.
Director, Education Group
Europe, Middle East, Africa
Dr. Martina A. Roth is Director of the Intel® Education Group for Europe, Middle East and Africa (EMEA). She is responsible for the development and implementation of all of Intel's Education Programs in the region, currently covering nearly 50 countries on three continents.
Dr. Roth joined Intel in 1997 as Program Manager for "Kids and Creativity" at Intel's Content Group, managing Intel Software Developers throughout Europe and providing leading edge Education content to the school and after school market.
In 1999 she became the Education Manager for Intel Central Europe, leading Intel's Education Programs like Intel® Teach to the Future, Intel® ISEF and Higher Education
in Germany, Austria and Switzerland. Following the success of the programs in the region, Dr. Roth has been appointed Intel Director of Education, for Europe, Middle East and Africa in 2002.
Prior to joining Intel Corporation, Dr. Roth was Methodic Director of the Management Training Center at Carl Zeiss Jena GmbH, Marketing and Multimedia Instructor at 3V Multimedia in Munich and scientific collaborator at the Friedrich Schiller University in Jena, Germany.
Dr. Roth holds a M.A. in Pedagogy and a Ph.D. in Philology from the University of Jena, Germany. She received an additional qualification as Media-Didactic and Lecturer for Learning Systems in Munich, attended a certified Market Strategy Course at INSEAD, Fontainebleau/France and Entrepreneurship Workshop from UC Berkley/US.
Dr. Roth is invited speaker at various international events e.g. the World Economic Forum, UN and UNESCO Conferences, Education Forums etc.
Dr. Roth is married and has two children.
Imre J. Rudas, graduated from Bánki Donát Polytechnic, Budapest in 1971, received the Master Degree in Mathematics from the Eötvös Loránd University, Budapest, the Ph.D. in Robotics from the Hungarian Academy of Sciences in 1987, while the Doctor of Science degree from the Hungarian Academy of Sciences.
He serves as the Rector of Budapest Tech from August 1, 2003. He is active as a full university professor and Head of Department of Intelligent Engineering Systems.
He is a Fellow of IEEE
, Administrative Committee member of IEEE Industrial Electronics Society, Vice-Chair of IEEE Hungary Section, Chairman of the Hungarian Chapters of IEEE Computational Intelligence and IEEE Systems, Man and Cybernetics Societies.
He is the President of the Hungarian Fuzzy Association, Vice-President of International Fuzzy System Association (IFSA), and Steering Committee Member of John von Neumann Computer Society.
His present areas of research activity are: Robotics with special emphasis on Robot Control, Soft Computing, Computed Aided Process Planning, Fuzzy Control and Fuzzy Sets. He has published one book, more than 300 papers in various journals and international conference proceedings.
Vice President, Corporate Technology Group
Director, Microprocessor Technology Lab
Joseph D. Schutz is vice president of the Corporate Technology Group and director of Microprocessor Technology Lab for Intel Corporation. Schutz is responsible for research for future microprocessors.
Schutz joined Intel in August 1981. He was a principle designer for the world's first CMOS DRAM, and led the design of the 256 Kbit CMOS DRAM. Schutz consulted on the design of the original i386T microprocessor. He co-managed the development of an i386T microprocessor and managed the development of an i486T processor. Subsequently, he was director of Microprocessor Design in the Portland Technology Development Group and co-managed four microprocessor designs within the Pentium® processor and Pentium® II processor families. He co-managed the Prescott microprocessor and managed the Cedar Mill microprocessor.
Before joining Intel, Schutz designed custom integrated circuits. He holds seven patents.
Schutz earned his bachelor's degree in Electrical Engineering from the University of Utah.
Director, Corporate Affairs Group
William A. Swope is corporate vice president and director of Intel's Corporate Affairs Group. Swope is responsible for enhancing Intel's position as the world's leading technology brand in business and corporate citizenship. Swope manages global business units at Intel and is responsible for worldwide public policy, education, community engagement, public affairs, social responsibility and the Intel Foundation.
Since joining Intel in 1979, Swope has held numerous roles including manufacturing technology planning, strategic product planning and product management. Swope was director of Digital Enterprise Brand Management, and prior to that he was general manager of the Software and Solutions Group (SSG), reporting to the president and chief operating officer of Intel. In that capacity he managed the software products and enabling efforts within SSG. From 1993 to 1995, Swope was the general manager of the Pentium® Pro processor team. Swope was promoted to vice president in 1996, and corporate vice president in 2003.
Swope received his bachelor's degree in applied physics from Tufts College. He earned his master's degree in management from Massachusetts Institute of Technology. Swope serves on the board of directors for iMove®, Inc.
Vice President, Corporate Technology Group
Director, Technology Policy and Standards
Donald M. Whiteside is vice president of the Corporate Technology Group and director of Technical Policy and Standards for Intel Corporation. Whiteside is responsible for coordinating Intel's efforts in development and management of technical policy and standards in support of Intel's global technology leadership objectives. The TPS organization influences global technical policy through facilitating Intel participation in global standards setting processes, industry alliances, public policy organizations, and legislative & regulatory agencies.
Prior to Whiteside's appointment as director, Technical Policy & Standards, he was director, Strategic Programs Office where he coordinated Intel's efforts in accelerating broadband and rich content deployment.
Whiteside received a bachelor's degree in Mathematics & Computer Science from Tulane University in 1981.
Intel Senior Fellow, Technology and Manufacturing Group
Director, Advanced Circuits and Technology Integration
Intel Senior Fellow Ian Alexander Young, an Intel employee since 1983, is the Director of Advanced Circuits and Technology Integration, Portland Technology Development, in Hillsboro. Ore. He is responsible for defining and developing future circuit directions and optimizing the manufacturing process technology for high-performance microprocessor and communications products.
Starting from development of circuits for a 1Megabit DRAM, he led the design of three generations of SRAM products and manufacturing test vehicles, and developed the original Phase Locked Loop (PLL) based clocking circuit in a microprocessor for the 50MHz Intel486T processor. He subsequently developed the core PLL clocking circuit building blocks used in each generation of Intel processors through the 0.13um 3.2 GHz Pentium 4, enabling them to leverage transistor speed improvements. This innovative clock circuit was one of the key factors for his promotion to Intel Fellow in 1996. Young has developed a number of optimization metrics for technology development, including the transistor performance metric (FEM) that provided a link between processor performance and basic transistor parameters. After development of a 10Gb/s SONET Serdes transceiver in the 90nm CMOS communications process, he recently led a small group of engineers to produce a world class CMOS Low Noise Amplifier and a wireless LAN RF/baseband Radio in 90nm CMOS.Young holds 34 patents. He has written more than 10 internal technical publications for the Intel Design Technology Conference, and Intel Technical Journal, as well as numerous external technical publications for IEEE journals.
Young has received three Intel Achievement Awards: In December 1996, "For development of a High Performance P856 Transistor 1.5 Years before Certification;" in April 1992, "For contributions made to the team defining and implementing a unique, cost effective approach to BiCMOS processing for Intel;" and in May 1991, "For the contribution made in the design of an analog PLL for 50-MHz Intel 486 microprocessor chip set. The functional C8 B-step silicon exceeds design requirements." He has also received divisional awards "for contributions to developing understanding of low power circuit design Best Known Methods and promoting attention to Energy and Speed trade-offs in design throughout the company" and "for exceptional support of LAD Gigabit PHY Analog debug and validation," from Intel's Microprocessor Products Group and Intel's Communications Group.
Born in Melbourne, Australia, in 1951, he received his bachelor's and master's degrees in Electrical Engineering from the University of Melbourne, Australia, in 1972 and 1975. He received his Ph.D. in Electrical Engineering from the University of California, Berkeley in 1978. Prior to Intel, Young worked on analog/digital integrated circuits for Telecommunications at Mostek Corporation, and did some consulting work.
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