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82562EZ(EX) and 82547GI(EI) Design Checklist v1.2

Project Name Fab Revision Date Designer Intel Contact Reviewer SECTION CHECK ITEMS Have up-to-date product documentation and spec General updates. Observe instructions for special pins needing pull- up or pull-down resistors. Connect LCI signals to corresponding signals on 82562EZ(EX) ICH device. LCI Device Option Each of the four control pins TESTEN, ISOL_TCK, ISOL_TI, and ISOL_EXEC should be connected to a LAN disable circuit through 100 Ω resistors. Use a 93C46 EEPROM for non-alerting applications or a 93C66 EEPROM for ASF 1.0. Note: DO NOT use a Catalyst 93C46 Revision H. √ REMARKS DONE Documents are subject to frequent change. Do not connect pull-up or pull-down resistors to any pins marked No Connect. Contact Intel for latest LAN disable circuit recommendations. If the LOM disable function is not used, connect Ball A13 to ground through a 3.3 K resistor. EEPROM for 82562EZ(EX) attaches to ICH. Add decoupling capacitor. EEPROMs should be rated for at least 1 MHz. Connect Ball B14 RBIAS10 to ground through a Recommended starting value. Meaure PCB's output amplitude and adjust as required to meet 619 Ω 1% resistor. IEEE specification. See the 82562EZ(EX)/82547GI(EI) Dual Footprint Design Guide for more information. Connect Ball B13 RBIAS100 to ground through a Recommended starting value. Meaure PCB's output amplitude and adjust as required to meet 649 Ω 1% resistor. IEEE specification. See the 82562EZ(EX)/82547GI(EI) Dual Footprint Design Guide for more information. COMMENTS Page 1 SECTION 82547GI(EI) Controller Option CHECK ITEMS Connect CSA interface pins to corresponding pins on MCH. REMARKS √ DONE Connect Ball G1 CI_CLK to a 66 MHz output of the host clock generator. Connect Ball N3 CI_RCOMP to 1.2 V through a 30.1 Ω resistor. Connect Ball P3 CI_SWING and Ball N4 CI_VREF to the specified voltage divider network on 1.2 V. Connect Ball A9 LAN_PWR_GOOD to RSM_RST# or other voltage supervisor circuit. Connect Ball A6 PME# to ICH for wake up signaling. Connect Ball J12 AUX_PWR signals correctly. Connect Ball B9 RST# to RST# on ICH. If a LAN disable function is required, drive Ball P9 FLSH_SO /LAN_ DISABLE#. Use a 93C46 EEPROM for non-alerting applications, an AT25040 for ASF 1.0, or an AT25080 for ASF 2.0. Note: DO NOT use a Catalyst 93C46 Revision H. Use a 33 Ω series resistor and a 10 pF bypass capacitor to ground. Do not adjust the values of the specified 1% tolerance resistors. Input should remain low until all power supplies are stable and for approximately 80 ms. LAN_PWR_GOOD works like an auxiliary chip reset. It should be a clean, glitch-free signal. It is not intended for use as a LAN Disable. LAN_PWR_GOOD must be asserted during powerdown states to allow wakeup. Typical connection is GPIO8. AUX_PWR is a logic input denoting that auxiliary power is connected to the device. AUX_PWR = 1 is a requirement for wakeup. Connect the controller’s LAN_DISABLE# to a Super IO general purpose (GP) output port that retains its value upon PCI reset. For Microwire* EEPROMs, install a 100 Ω pull- down resistor on Ball Read the full 82562EZ(EX) and 82547GI(EI) Design Checklist v1.2.

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