This document describes the external architecture (including device operation, pin descriptions, register definitions, and more) for the Intel® Ethernet Controller X540 (X540), a dual port 10GBASE-T Network Interface Controller.
This document is intended as a reference for logical design group, architecture validation, firmware development, software device driver developers, board designers, test engineers, or anyone else who might need specific technical or programming information about the X540.
The Intel Ethernet Controller X540 is a derivative of the 82599, the Intel® 10 GbE Network Interface Controller (NIC) targeted for blade servers. Many features of its predecessor remain intact; however, some have been removed or modified as well as new features introduced.
The Intel Ethernet Controller X540 includes two integrated 10GBASE-T copper Physical Layer Transceivers (PHYs). A standard MDIO interface, accessible to software via MAC control registers, is used to configure and monitor each PHY operation.
Read the full Intel® Ethernet Controller X540: Datasheet.