Intel’s Chris Clark shows how HyperScan* software enhances content inspection by efficient matching of large data sets and patterns at RSA 2014.
Intel DPDK Architect Chris Clark demonstrates how HyperScan* software supported by Intel® multi-core processors enhances content inspection by efficiently matching large amounts of data and patterns at the RSA Conference 2014.
Explains how packet processing on Intel® architecture and Intel® Data Plane Development Kit improve standard high-volume server performance.
Intel Software Product Line Manager Jim St. Leger explains how Intel® Data Plane Development Kit and packet processing on Intel® architecture improve performance for standard high-volume servers and network function virtualization.
Wind River INP* software on Intel® architecture demo shows flexibility, security, and speed benefits for application packet management at RSA 2014.
Wind River INP* software on Intel® architecture with Intel® Data Plane Development Kit demo for packet management in applications shows flexibility, security, and speed benefits while reducing total cost of ownership at RSA 2014.
Reiher and Kaiser, UCLA, discuss Intel® Atom™ LEAP* architecture and embedded systems instructions for energy efficiency.
Software: Provides the source code verilog RTL files for the system management controller CPLD for Little Bay Fab D/Fab E boards with Intel® Atom™ processor E6xx series B0/B1 stepping; includes release note, checksum, QUARTUS, and SRC files.
Legacy power management features on Intel® architecture-based platforms for embedded systems, including various states. (v.001, Aug. 2011)
Overview of the legacy power management features on Intel® architecture-based platforms for embedded systems, including performance, processor, thermal, and system states. (v.001, Aug. 2011)