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Data Plane Packet Processing Embedded Intel® Architecture: Paper

White Paper: Discusses techniques for overcoming challenges to achieve high-performance data plane packet processing on embedded Intel® architecture.

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Pattern Matching Performance with HyperScan* Software: Brief

Solution Brief: Discusses pattern matching performance optimization of Sensory Networks HyperScan* software with Intel® Xeon® processors.

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Intel® Xeon® Processor E5-2600 Series for Intelligent Systems

Platform Brief: Ideal for Intelligent Systems, the security-focused embedded platform enables device connectivity to networks, clouds, and each other.

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AES CBC Encrypt/Decrypt for Sandy Bridge

Source Code: AES CBC Encrypt Multibuffer / Decrypt Single Buffer optimized for Sandy Bridge

Intel® Data Plane Development Kit Optimizes Packet Processing

Presentation: The Intel® Data Plane Development Kit enables multi-workloads on single architecture optimized for packet processing. (v.001, Dec. 2012)

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Software: Fast CRC16 Code for T10 DIF

Software: Use this optimized function to compute a 16-bit cyclic redundancy check as defined in the T10 DIF standard using PCLMULQDQ instruction.

Modular Exponentiation Source Code for Packet Processing: Release

Code Release: Implement assembly source code of constant-time modular exponentiation for cryptographic algorithms and packet processing.

Intel® Multi-Buffer Crypto for IPSec: Install Package

Install Package: Download the Intel® Multi-Buffer Crypto for IPSec, including a comprehensive library of functions for different Intel® architectures.

Media Processing

As mobile devices become more sophisticated, innovative architecture from Intel helps improve the user experience.

Intel® Hardware-Based Technologies for Intelligent Systems

Discover hardware-based technologies that lower costs, increase security, and simplify the management of intelligent systems. (v.1, Aug. 2013)