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PCI Express* Architecture

The Intel developer network for PCI Express* architecture is a developer community offering access to resources and peers.

PCI Express* Architecture

PCI Express* Architecture is a standards-based serial data, multi-lane interconnect for high-performance, scalable interconnects.

Serial ATA AHCI: Specification, Rev. 1.1

Defines functional behavior and Advanced Host Controller Interface software for moving data between system memory and serial ATA devices.

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Serial ATA AHCI: Specification, Rev. 1.2

Defines functional behavior and Advanced Host Controller Interface software for moving data between system memory and serial ATA devices.

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Serial ATA AHCI: Device Sleep Technical Proposal, Rev. 1.3.1

Programming register definitions, a method to detect support for direct software control, and a method for HW to autonomously enter and exit DevSleep.

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PCI Express* Architecture

PCI Express* Architecture is a standards-based serial data, multi-lane interconnect for high-performance, scalable interconnects.

USB 3.0* Radio Frequency Interference on 2.4 GHz Devices

White Paper: Notice of certain USB 3.0* devices and cables causing radio frequency interference to wireless devices operating in the 2.4 GHz ISM band.

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PCI Express* Architecture Power Management Rev 1.1

White Paper: Power management guidelines for PCI Express* links on Intel®-based Mobile platforms.

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USB 3.0 Internal Connector and Cable Specification

Internal cable interface for USB 3.0 in desktops, focuses on electrical and mechanical requirements of the connector and cable assembly.

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