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® Intel 82579 Reference Schematic v2.1

+3.3V_A +3.3VS If CLK_REQ_N is connected to R5 R73 R72 PCIECLKRQ[1:2]#, the CLK_REQ_N 10K 2.2K 2.2K pull-up resistor should be connected to +V3.3S. For non-Mobile EU4 R69 is no stuff R69 0 MDI0P 48 13 PCIECLKRQ5# CLK_REQ_N MDI_PLUS0 MDI0N 36 14 R6 0 PLTRST# PE_RST_N MDI_MINUS0 MDI1P 44 17 PE_CLKP MDI_PLUS1 CLKOUT_PCIE5P MDI1N 45 18 CLKOUT_PCIE5N PE_CLKN MDI_MINUS1 PCIE MDI MDI2P 38 20 C3 0.1uf R13 0 PERp[1:8] PETp MDI_PLUS2 MDI2N 39 21 C4 0.1uf R14 0 PERn[1:8] PETn MDI_MINUS2 MDI3P 41 23 0.1uf C70 R89 0 PETp[1:8] PERp MDI_PLUS3 MDI3N 42 24 0.1uf C71 R90 0 PERn MDI_MINUS3 PETn[1:8] +3.3V_LAN close to PHY close to PCH 28 6 N/C SML0CLK SMB_CLK RSVD_NC SMBUS 31 SMB_DATA SML0DATA 12 R87 4.7K RSVD_VCC3P3_1 R88 4.7K RSVD_VCC3P3_2 5 +3.3V_LAN VDD3P3_IN LAN_DISABLE_N_R 3 LAN_DISABLE_N NOTE: R15 pull-up resistor has been 4 VDD3P3_OUT +3.3V_LAN changed to "NO_STUFF" from last C75 15 VDD3P3_15 LED0 rev2.0. Pull-up is not required. 26 19 1uf LED0 VDD3P3_19 R15 LED1 29 27 Existing designs that have this VDD3P3_29 LED1 R83 R93 10K LEDDOCKED LED2 25 LED2 10K NO_STUFF 10K pull-up populated do not need to NO_STUFF 1.05Vdc NO_STUFF 47 VDD1P0_47 change. Both "NO_STUFF" and 46 VDD1P0_46 37 32 "POPULATED" configurations have been VDD1P0_37 JTAG_TDI 34 JTAG_TDO validated and are supported. JTAG43 33 VDD1P0_43 JTAG_TMS 35 Keep JTAG_TCK 11 R70 0 VDD1P0_11 LAN_DISABLE_N short R36 0ohm 40 9 VDD1P0_40 XTAL_OUT and wide NOTE: LAN_DISABLE_N must be 22 10 Y3 R16 VDD1P0_22 XTAL_IN 16 10K connected to GPIO12/LAN_PHY_PWR_CTRL VDD1P0_16 8 NO_STUFF VDD1P0_8 L1 30 output of PCH to ensure proper LAN 25MHz TEST_EN 4.7uH C8 C7 functionality. This GPIO12 pin must 12 7 33pf 33pf RBIAS CTRL_1P0 be set as "LAN_PHY_PC" function Idc_min=500mA 49 DCR=100mohm VSS_EPAD through FITC tool. 82579 R27 R17 3.01K, 1% 1K LED0 LED1 LED2 1.05V_SHARED Place R80, C68, R80 0 C69, size 805 NO_STUFF and L1 close to PHY C68 22uf C69 0.1uf Note: C68 can be replaced by two 10uF caps (total 20uF minimum requirement). +3.3V_A +3.3V FET OUT Switch +3.3V_ML 1.05Vdc POWER OPTIONS Internal SRV Shared with PCH's 1.05V SVR* STUFF: L1 STUFF: R80 NO STUFF: L1 NO STUFF: R80 *NOTE: 1.05Vdc can be shared from PCH's 1.05V SVR (typically the ME rail). When sharing, make sure both +3.3V_LAN & 1.05Vdc rails are remained powered on during ALL Sx states, as required to support WOL. +5.0V_A 1.05V SVR OUT (for PCH) 1.05V_SHARED SLP_LAN# *IMPORTANT NOTE: SLP_LAN# Control PHY Powers +3.3V_ML 0805 R74 0 +3.3V_LAN C73 22uf C74 0.1uf Note: C73 & C74 close to PHY 2 3 7 8 11 12 14 15 19 20 54 17 1 6 9 13 16 21 24 28 33 39 44 49 53 55 A0 A1 A2 A3 A4 A5 A6 A7 LED0 LED1 LED2 SEL GND GND GND GND GND GND GND GND GND GND GND GND GND GND U6A 0B1 0B2 1B1 1B2 2B1 2B2 3B1 3B2 4B1 4B2 5B1 5B2 6B1 6B2 7B1 7B2 0LED1 0LED2 1LED1 1LED2 2LED1 2LED2 48 46 47 45 43 41 Read the full ® Intel 82579 Reference Schematic v2.1.

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