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8 F E 7 6 5 4 3 REFERENCE DESIGN PCIE SINGLE LANE 1000/100/10 BASE-T INTEL 82574 ETHERNET CONTROLER 2 1 F E D D C C B B A 8 7 INTEL LAN ACCESS DIVISION 2111 N.E. 25th AVENUE HILLSBORO, OR 97124 6 TITLE 82574 REFERENCE DESIGN 5 4 SIZE CODE DOCUMENT NUMBER 3 2.1 REV 2 08-04-2008 DATE SHEET 1 1 A PAGE2 8 F E FUNCTIONAL BLOCK DIAGRAM 7 6 5 4 3 2 1 F E D D C C B B A 8 7 INTEL LAN ACCESS DIVISION 2111 N.E. 25th AVENUE HILLSBORO, OR 97124 6 TITLE 82574 REFERENCE DESIGN 5 4 SIZE CODE DOCUMENT NUMBER 3 2.1 REV 2 08-04-2008 DATE SHEET 1 2 A PAGE3 8 F 7 6 5 E D C POWER BLOCK DIAGRAM JUMPER_TABLE ON_SHEET_08 4 3 2 1 F E D C B B A 8 7 INTEL LAN ACCESS DIVISION 2111 N.E. 25th AVENUE HILLSBORO, OR 97124 6 TITLE 82574 REFERENCE DESIGN 5 4 SIZE CODE DOCUMENT NUMBER 3 2.1 REV 2 08-04-2008 DATE SHEET 1 3 A PAGE4 F E PCIE X1 LANE EDGE CONNECTOR WITH 82574'S CLOCKING, RECV, XMIT AND RESET SIGNAL INTERFACE 2 8 7 6 5 4 3 PCIE_3.3V_AUX 1 C87 10UF 6.3V 2 20% 0805LF 1 C89 10UF 6.3V 2 20% 0805LF PLACE THESE CAPS CLOSE TO EDGE CONNECTOR PCIE_3.3V_MAIN 1 7E1<> 7E1<> D BI BI SMB_CLK SMB_DAT 5E1> IN PE_WAKE_N 1% 0 1206LF CHIP 1/2W1 2 R64 R65 1 2 0 1% 1/2W 1206LF CHIP C B 1 1 C86 C88 10UF 10UF 6.3V 6.3V 2 2 20% 20% 0805LF 0805LF NC_12V J5 I73 B12 A1 B A23 B3 A NC_1 B4 A4 B5 A56 NC_JTAG2 B6 A JTAG TDO TIED TO TDI TO CREATE LOOP THROUGH AT EDGE CONNNECTOR B7 A78 B8 A NC_JTAG5 B9 A910 NC_JTAG1 B10 A B11 A11 B12 A12 NC_2 REFCLKP B13 A13 REFCLKN B14 A14 A15 B156 A16 B1 A178 B17 B18 A1 CONTROLLER PCIE DIFFERENTIAL PAIRS CAN BE POLARITY(PN) SWAPPED TO OPTIMIZE ROUTING PCIE DIFFERENTIAL LAN PAIRS CAN BE POLARITY(PN) 82574 SWAPPED TO OPTIMIZE ROUTING ROUTE PECLK SIGNALS TO AS DIFFERENTIAL PAIRS SIGNALS PER PCIE SPECIFICATION DIFFERENTIAL ROUTE PE_R PE_RSIGNALS AS DIFFERENTIAL PAIRS PER PCIE SPECIFICATION PE_R_P PE_R_N 82574'S CLOCKING, RECIEVE, TRANSMIT AND RESET SIGNAL INTERFACE ---> FCONN36_PCI_EXPRESSX1 12V1 PRSNT1A_N 12V2 12V3 RSVD1 12V4 GND1 GND35 SMCLK JTAG2 SMDAT JTAG3 GND2 JTAG4 3_3V1 JTAG5 JTAG1 3_3V2 3_3VAUX 3_3V3 WAKE_N PERST* KEY RSVD2 GND36 GND3 REFCLKP REFCLKN PETP[0] GND37 PETN[0] GND4 PERP[0] PRSNT2_N PERN[0] GND38 GND5 PCIE DIFFERENTIAL PAIRS CAN BE POLARITY(PN) SWAPPED TO OPTIMIZE ROUTING CONTROLLER LAN 82574 ROUTE PE_T SIGNALS AS DIFFERENTIAL PAIRS ON BOTH SIDES OF CAPACITORS FROM PER PCIE SPECIFICATION SIGNALS DIFFERENTIAL C46 0.1UF 10V PE_T 10% X5R 0402LF 1 2 21 PE_T_P 24 PE_T_P_CAP 20 23 1 2 PE_T_N PE_T_N_CAP 17 0.1UF X5R 0402LF 265 10V 2 10% I97 C50 IC EU1 LCCLF PLACE_THESE_CAPACITORS CLOSE_TO_PE_T_SIGNALS_OF_DEVICE 82574l PE_Rp PE_Tp PE_Rn PE_Tn PE_RST_N PECLKp PECLKn F E D C B A 8 7 INTEL LAN Read the full PAGE1.

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