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Intel® 82573E/V/L Layout Checklist (version 1.5)

Project Name Fab Revision Date Designer Intel Contact SECTION General Ethernet Devices CHECK ITEMS REMARKS Obtain the most recent documentation Documents are subject to frequent and specification updates change √ DONE Route the transmit and receive differential traces before routing the digital traces. Place the Ethernet silicon at least 1 inch from the edge of the board. Layout of differential traces is critical. With closer spacing, fields can follow the surface of the magnetics module or wrap past edge of board. EMI may increase. Optimum location is approximately 1 inch behind the magnetics module. Place the silicon at least 1 inch from the integrated magnetics module but less than 4 inches Keep trace length under 4 inches from the Ethernet controller through the magnetics to the RJ-45 connector. Signal attenuation will cause problems for traces longer than 4 inches. However, due to EMI, the silicon should be placed at least 1 inch away from the magnetics module. Place the AC coupling capacitors on the PCIe* Tx traces as close as possible to the 82573E/V/L but not further than 250 mils. For the 82573 controller, ensure the trace impedance for the PCIe* differential pairs is 100 Ω +/- 20%. Match trace lengths between PCIe* pairs to within 3 inches. Size 0402, X7R is recommended. The AC coupling capacitors should be placed near the transmitter for PCIe*. These traces should be routed differentially. Match trace lengths within each PCIe* pair on a segment-by-segment basis. Match trace lengths within a pair to 5 mils. Place crystal and load capacitors within This reduces EMI. Clock Source 0.75 inches of the Ethernet device. Match the length of the clock lines to A large difference in length between the within 200 mils. clock lines leads to clock skew. Keep clock lines away from other This reduces EMI. digital traces (especially RESET signals), I/O ports, board edge, transformers and differential pairs Ensure that traces meet the EEPROM and Flash can be placed a few Non-Volatile specifications of the design guide inches away from Ethernet controller to Memory (placement is not critical). Refer to the provide better spacing of critical design guide for routing specifications components. for particular stackups. COMMENTS 1 Place 47Ω damping resistors on the NVM lines close to the signal driver. 0.1inches is recommended. Please refer to the design guide for all length requirements. For both shared and dedicated NVM configuration options, place 0 Ω resistors to minimize the stubs on the NVM lines for each option. Primary requirement for 10/100/1000 Transmit and Design traces for 100 Ω differential Mb/s Ethernet. Paired 50 Ω traces do not impedance (± 20%) Receive Differential make 100 Ω differential. An impedance calculator can be used to verify this. Pairs Avoid highly resistive traces (for If trace length is a problem, use thicker example, 4 mil traces longer than 4 board dielectrics to allow wider traces. inches) Thicker copper is even better than wider traces. Make traces symmetrical Pairs should be matched at pads, vias and turns. Rules for Read the full Intel® 82573E/V/L Layout Checklist (version 1.5).

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