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Intel® 82573 Schematic Checklist (version 1.6)

Project Name Fab Revision Date Designer Intel Contact Reviewer SECTION General 82573 Controller CHECK ITEMS REMARKS Obtain the most recent documentation Documents are subject to frequent and specification updates change √ DONE Observe instructions for special pins needing pull-up or pull-down resistors Connect PCIe* interface pins to corresponding pins on ICH Place AC coupling capacitors (0.1µF) near the PCIe* transmitter Connect balls G2 PE_CLKn and G1 PE_CLKp to 100 MHz PCIe* system clock Connect PE_RST# to PLTRST# on the ICH Connect PE_WAKE# to PE_WAKE# on the ICH Connect ball P5 LAN_PWR_GOOD to RSMRST# on the ICH Connect ball L7 DEVICE_OFF# to SUPER_IO_GP_DISABLE# Do not connect pull-up or pull-down resistors to any pins marked No Connect, Test, or Reserved. Connect to the reset supervisor for the LAN power well Connect to a super I/O pin that retains its value during PCIe* reset, is driven from the resume well and defaults to one on power-up. If not connected to a super I/O pin, then Device_Off# should be connected with an external pull-up resistor. Pull-down ball D12, PHY_REF, with a 4.99 KΩ 1% resistor Pull-down ball A13 TEST_EN with a 3.3 KΩ resistor Leave ball C3, DOCK_IND, unconnected. This feature is not supported in the 82753. 82573L only: Connect ball P9, 82573L only: This signal may be left CLKREQ#, to the clock driver unconnected if functionality is not desired responsible for generating the PCIe* but functionality must also be disabled in clock. the NVM. Ensure that ball C6, AUX_PRESENT (AUX_PWR for the 82573L), is pulled- up to the 3.3V standby power supply if the LAN Controller is powered from standby supplies. This signal should be pulled down if auxiliary power is not used. Use 25 MHz 30 ppm accuracy@ 25 °C Parallel resonant crystals are preferred. Clock Source clock source. Avoid components that A clock oscillator can be used if introduce jitter. testability rules require turning off the clock. If an oscillator is used, consider a series termination resistor of 22-33 Ω. Avoid PLL clock buffers. Connect two 22 pF load capacitors to Capacitance affects accuracy of the the crystal. frequency. Must be matched to crystal specifications, including estimated trace capacitance in calculation. 1 COMMENTS Applies to EEPROM or FLASH devices. EEPROM and Use 0.1 µF decoupling capacitor FLASH Connect WP# and HOLD# signals to Applies to EEPROM or FLASH devices. Memory VCC through a 3.3 KΩ resistor For shared Flash configuration, connect ball D3 NVM_SHARED to ground through a 3.3 KΩ resistor If SPI Flash is used, connect ball A6 NVM_TYPE to ground through a 3.3 KΩ resistor To disable SPI NVM protection, install a jumper to connect ball A5 NVM_PROT to ground Connect ball B4 NVM_REQ to If both shared and dedicated SPI_ARB on the ICH. This signal configuration options are available please should be unconnected for dedicated use a 0 Ω stuffing option for this signal. LAN Flash configuration. Check EEPROM connections to NVM_CS#, NVM_SK, NVM_SI, NVM_SO For dedicated LAN Flash: The 47Ω resistors should be placed - Connect NVM_CS# Read the full Intel® 82573 Schematic Checklist (version 1.6).

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