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82545GM Gigabit Ethernet Controller Networking Silicon Datasheet Product Features

• PCI/PCI-X —PCI-X Revision 1.0a support for frequencies up to 133 MHz —Multi-function PCI device —PCI Revision 2.3 support for 32-bit wide or 64-bit wide interface at 33 MHz and 66 MHz • MAC —IEEE 802.3x compliant flow control support with software controllable pause times and threshold values —Programmable host memory receive buffers (256 Bytes to 16 Kbytes) and cache line size (16 Bytes to 256 Bytes) —Wide, optimized internal data path architecture (128 bits) —64 Kbyte configurable Transmit and Receive FIFO buffers —Optimized descriptor fetching and write- back mechanisms • PHY —Integrated PHY for 10/100/1000 Mbps full and half duplex operation —IEEE 802.3ab Auto-Negotiation support —IEEE 802.3ab PHY compliance and compatibility —PHY ability to automatically detect polarity and cable lengths and MDI versus MDI-X cable at all speeds • Host Offloading —Transmit and receive IP, TCP and UDP checksum off-loading capabilities —Transmit TCP segmentation —IEEE 802.1q VLAN support with VLAN tag insertion, stripping and packet filtering for up to 4096 VLAN tags —Advanced packet filtering • Manageability —Manageability features on both ports: SMB port, ASF 1.0, ACPI, Wake on LAN, and PXE —Compliance with PCI Power Management 1.1 and ACPI 2.0 register set compliant • Four activity and link indication outputs that directly drive LEDs a • Lead-free 364-pin Ball Grid Array (BGA). Devices that are lead-free are marked with a circled “e1” and have the product code: PCxxxxxx. a. This device is lead-free. That is, lead has not been intentionally added, but lead may still exist as an impurity at <1000 ppm. The Material Declaration Data Sheet, which includes lead impurity levels and the concentration of other Restriction on Haz- ardous Substances (RoHS)-banned materials, is available at: ftp://download.intel.com/design/packtech/material_content_IC_Package.pdf#pagemode=bookmarks In addition, this device has been tested and conforms to the same parametric specifications as previous versions of the de- vice. For more information regarding lead-free products from Intel Corporation, contact your Intel Field Sales representative. 322559-001 Revision 2.2 August 2009 Revision History Revision 1.0 1.1 1.2 1.5 2.0 2.1 2.2 Date Mar 2003 Nov 2003 Sept 2004 June 2005 Sept 2005 Feb 2007 Aug 2009 Description Initial release. Removed Confidential Status. Modified power specification tables in Section 4.0. Added a ball pad dimension drawing for the 82545GM device in Section 5.0. Corrected the nominal impedance values for the I/O cells from 50 kohms to a nominal impedance value of 120 kohms, with a minimum of 90 kohms and a maximum of 190 kohms. Added Specification Change and Specification Clarification information from the 82545GM Gigabit Ethernet Controller Specification Update. Added a more detailed AUX_PWR pin description. Added tristate and XOR non-JTAG test modes description. Added lead free information. Updated Table 3. Updated section 5.2, table 3. Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or Read the full 82545GM Gigabit Ethernet Controller Networking Silicon Datasheet Product Features.

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