Covers uncore performance monitoring registers, counters, and integrated memory controller specifics.
Demonstrates the cost-saving benefits of remote management capabilities. (v.1, Sept. 2010)
Demonstrates verification using turbo mode gadget and frequency display utility. (v.1, Oct. 2010)
Demonstrates how to use open source hypervisor, Xen* 3.0, and CentOS* 5.5. (v.1, Oct. 2010)
Describes advantages for embedded performance, security, and reliability. (v.1, Jan. 2011)
Learn about using the right tools with a symmetric multi-processing real-time OS. (v.1, Jan. 2011)
Demonstrates how to use a USB drive to boot a customer reference board to DOS. (v.1, June 2010)
Demos set-up, software, oscilloscope settings, and power delivery assessments. (v.001, Mar. 2010)
Demos tools, oscilloscope, platform, waveform analysis, SigTest software, and reports. (v.001, Mar. 2010)
Highlights processor intelligence and scalability for low-power, high performance solutions.
Webinar details AltiVec* SIMD macros translator migration to Intel® processors. (v.1, May 2009)
A discussion of experimental techniques for rapid mitigation of phishing and spam. (v.1 June 2009)
Research on building a network device for improving peer-to-peer traffic control. (v.1, June 2009)
Discusses increasing throughput for multi-core processors. (v.1, June 2009)
External Design Specification: Electrical, signal, and thermal specs, definitions. (v.002.2, July 2012)
External Design Spec, Vol. 2: Configuration registers for two processor families. (v.2.1, May 2012)
Schematic: Provides the Cadence* and OrCAD* schematic symbol files.
Platform Design Guide: Recommendations for platform controller hub and system memory. (v.2.1, April 2012)
Anteriormente Carlow (Ivy Bridge + Panther Point)
Anteriormente Chief River (Ivy Bridge + Panther Point)
El controlador es ideal para diseños de factor de formato pequeño y LAN de cliente/servidor en configuraciones de board.
Anteriormente Maho Bay (Ivy Bridge + Panther Point)