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Logic Paper: 32nm logic technology for high performance microprocessors
Presentation: low power optimization for a 32nm SoC platform with 2nd generation high-k/Metal gate transistors.
Brief examines the impacts and benefits of RF CMOS technology scaling in high-k/Metal gate era for RF SoC (System-on-Chip) applications.
Presentation examines the impacts and benefits of RF CMOS technology scaling in high-k/Metal gate era for RF SoC (System-on-Chip) applications.
Presentation: Tahir Ghani (Intel) reviews traditional‐scaling, modern innovations and future challenges and options for Nano‐CMOS Transistor Scaling.
Presentation discusses high performance 40nm gate length in Sb P-channel compressively strained QWFET for low power logic applications.
RF CMOS technology benefits from general CMOS technology scaling and improves by innovative transistor and interconnect technologies.
Presentation covers SiO2 scaling, high-k/metal-gate problems, breakthroughs, and performance reports for NMOS and PMOS transistors.
Article, IEEE Election Device Letters, Vol 25, No. 6, June 2004: High-k/Metal-Gate Stack and Its MOSFET Characteristics.
Paper examines and evaluates logic performance of Schottky-gate QWFETs against that of advanced Strained Si MOSFETs in low power voltages.
Intel introduces new 22nm technology.
Backgrounder: Intel's 22nm innovation ushers in new semiconductor technology and ensures the continuation of Moore's Law.
Presentation of 32nm logic technology for high performance microprocessors featuring 2nd generation high-k + metal gate transistors.
Paper covers optimization for a 32nm SoC platform with 2nd Generation high-k/Metal gate transistors.
Gate Dielectric Scaling for High-Performance CMOS: SiO2 to High-K, an option for the 45nm high-performance logic technology node.
Demonstrates a Germanium p-channel QWFET with thin scaled TOXE and high mobility, delivering four times higher hole mobility.
Paper: n-type and p-type metal electrodes on high-K gate dielectrics enable same oxide thickness, desirable transistor threshold, and more.
Paper: composite high-K gate in the QWFET silicon substrate integration for thin electrical oxide, low gate leakage, and carrier confinement.
Discusses 64-bit desktop computing benefits from more physical and virtual applications.