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Exceptional scalable performance with advanced reliability for your most data-demanding applications
Resources and Tools for hardware development & design using Intel® products and technologies.
Discusses 64-bit desktop computing benefits from more physical and virtual applications.
Built-In Hardware Features in Xeon® processor E7 family to minimize downtime and data loss; designed for more stability and scalability.
Intel® Xeon® Xeon® processor E3 for small business needs allows workload migratation and server consolidation.
Intel® Xeon® processor E7 family specifications
The Intel® E8500 Chipset is the highest performing, most scalable platform offering in the 64-bit Intel® Xeon® processor family.
Product Brief: Intel® 10 Gigabit AF DA Dual Port Server Adapter offers low-cost, "in-the-rack" connections, more performance, and energy efficiency.
Intel® PRO/1000 PT Dual Port Server Adapter with 10/100/1000 Mbps self-configuration for compatibility with mixed-speed network devices.
Product Brief: Intel® PRO/1000 PT Quad Port Server Adapter with 10/100/1000 Mbps connections for slot-constrained servers.
Intel® PRO/1000 MT Dual Port Server Adapter conserves valuable PCI slot space in servers.
Product Brief: Intel PRO/1000 PT Quad Port LP Server Adapter in a low-profile PCI Express* slot improves server throughput and rack density.
Packaging Databook, Ch. 1: Introduction of package families, including package attributes, package types, and a package selection guide.
Packaging Databook, Ch. 3: packaging technologies for assembling three types of component packages for alumina and leaded molded technology.
Packaging Databook, Ch. 4: basic package modeling terminology, methodology, and experimental characterization, and modeled data for the packages.
Packaging Databook Ch 7: leaded surface mount technology enables more reliable assemblies with higher I/O, board density, and less weight and cost.
Packaging Databook, Ch. 10: product and transport media, environmental programs, tape and reel, protective bands, and shipping formats.
Packaging Databook, Ch. 14: ball grid array packaging with electrical modeling, performance, and physical structure.
Packaging Databook, Ch. 16: The Single Edge Contact Cartridge and its physical structure, electrical modeling, and performance.
Packaging Databook, Ch. 15: chip scale package, physical structure, electrical modeling, and performance.
Application Note: how to use the CPUID instruction in software applications, BIOS implementations, and various processor tools.