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Gate Dielectric Scaling for High-Performance CMOS: SiO2 to High-KWe have successfully demonstrated very high-performance PMOS and NMOS transistors with high-K/metal-gate gate stacks with the right threshold voltages for both p- and n-channels on bulk Si. We believe that high-K/metal-gate is an option for the 45nm high-performance logic technology node.Introduction: The silicon industry has been scaling SiO2 aggressively for the past 15 years for low-power, high-performance CMOS logic applications. SiO2 as thin as 1.2nm (physical Tox) has already been successfully implemented in the 90nm logic technology node. Research transistors with 0.8nm SiO2 have also been demonstrated in the laboratory. However, continual gate dielectric scaling will require high-K, as SiO2 will eventually run out of atoms for further scaling. Most of the high-K gate dielectrics investigated are Hf-based and Zr-based. Both polySi and metals are being evaluated as gate electrodes for the high-K dielectrics. There are many challenges reported in literature in replacing SiO2 with high-K for high-performance CMOS. This paper will present results on the 0.8nm SiO2 and very high-performance PMOS and NMOS transistors with high-K/metal-gate for high-performance logic applications.Read the full Gate Dielectric Scaling for High-Performance CMOS SiO2 to High-K Paper.
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