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Gate Dielectric Scaling for CMOS: SiO2/PolySi to High-K/Metal-Gate

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• 1.2nm physical SiO2 in production in our 90nm logic technology node
• 0.8nm physical SiO2 in our research transistors with 15nm physical Lg
• Gate leakage is increasing with reducing physical SiO2 thickness
• SiO2 running out of atoms for further scaling
• Will eventually need high-K