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RF CMOS Technology Scaling in High-k/Metal Gate Era

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RF CMOS Technology Scaling in High-k/Metal Gate Era


The impact of silicon technology scaling trends and the associated technological innovations on RF CMOS device characteristics are examined. The application of novel strained silicon and high-k/metal gate technologies not only benefits digital systems, but significantly improves RF performance. The peak cutoff frequency (fT) doubles from 209 GHz in the 90 nm node to 445 GHz at the 32 nm node. 1/f flicker noise reduces by an order of magnitude from the 0.13 um node to the 32 nm node. Transistor noise figure, high voltage tolerance, and quality factors of RF passives all show similar benefits from technology scaling.


As silicon technology scaling progresses to the 32 nm node, single chip integration of RF and communication designs with the micro-processor cores on a common CMOS system-on-chip (SOC) platform has become increasingly appealing. This increased attention to RF SOC is driven by both the huge improvements in device performance afforded by Moore’s Law and by the advantage of higher vertical integration and lower manufacturing cost of mainstream CMOS technology. Modern technology scaling, however, is no longer a simple matter of shrinking device dimensions. Today’s technology scaling is enabled by introducing disruptive, innovative materials and novel device structures. Examples of these innovations include strained silicon and high-k/metal gates for transistors and low-k ILD and Cu metallization in the backend. The impact of these new inventions to mixed signal/RF designs needs to be examined with the intent to identify the true promise and challenges of radio integration into a general SOC platform.

Read the full RF CMOS Technology Scaling in High-k/Metal Gate Era Paper.