Seungjoon Park is a Senior Staff Research Scientist within Intel's Microprocessor and Programming Research Labs in Santa Clara, California. He has been working on definition and formal verification of scalable cache coherence protocols and their performance evaluation for many-core microprocessor architecture. He has also worked on FPGA designs of various cache architectures and on-chip interconnects for CMPs.
Prior to Intel, he was in the High-Assurance Software Design Research team at NASA Ames Research Center working on the project Java PathFinder, a system to verify executable Java bytecode programs. The team won NASA's TGIR Engineering Innovation Award for the year 2003.
He received his PhD in Electrical Engineering with minor in Computer Science from Stanford University, where he investigated Stanford FLASH multiprocessor’s cache coherence protocol and developed operational memory models of SPARC V9 architecture. He has published more than twenty journal articles and research papers, and co-authored a book chapter in SPARC Architecture Manual Version 9 (ISBN 0-13-099227-5) with SPARC committee.