Since 2007, Matthias Gries is working on architectures and design methods for memory subsystems and resource management at Intel Labs, Germany. He was a member of the design teams for Intel Labs’ Single-chip Cloud Computer (SCC) experimental 45nm manycore CPU and the FPGA-based DDR3 Programmable Memory Traffic Analyzer. Before, he spent three years at Infineon Technologies in Munich, Germany, working on microarchitectures for network applications at the Corporate Research and Communication Solutions departments. He was a post-doctoral researcher at the University of California, Berkeley, in the Computer-Aided Design group, developing design methods for application-specific programmable processors from 2002 to '04. He received the Doctor of Technical Sciences degree from the Swiss Federal Institute of Technology (ETH) Zurich in 2001 for his work on system-level design of a QoS network processor. He has published more than 40 papers and holds four patents.
His interests include architectures, methods and tools for platforms and application-specific systems, memory subsystems, and system-level design.