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Single Chip Cloud External Architecture: Specification

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The Single-chip Cloud Computer (SCC) is a 48-core Intel Architecture (IA) many-core experimental processor prototype. It is a research chip built to study many-core CPUs, their architectures, and the techniques used to program them. The research has the following goals:
1. To demonstrate a shared memory message-passing architecture for a large number of cores and to experiment with its programmability and scalability.
2. To design and explore the performance and power characteristics of an on-die 2D mesh fabric.
3. To explore the benefits and costs of software-controlled dynamic voltage and frequency scaling for multiple cores.

The IA core on the SCC is based on the P54C core. The 48 cores are placed in a tile formation, two cores to a tile. The tiles are connected by a 6x4 2D fully synchronous mesh fabric with rigorous performance and power requirements.

The SCC has multiple voltage and frequency domains, some configurable at startup, others that may be dynamically varied for application-controlled fine grain dynamic power and performance management.

The SCC die has four on-die memory controllers capable of addressing a total of up to 64GB of external memory. It also has a small amount of fast local memory located in each tile. Message- passing support is provided that use shared regions of local memory or off-die main memory. The SCC has a new memory type and a new processor cache instruction to facilitate memory management.

Read the full Single Chip Cloud External Architecture Specification.