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Ct: Flexible Parallel Programming for Tera-scale Architectures

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New Opportunities, New Challenges

Processor architecture is evolving towards more software-exposed parallelism through two features: multiple cores and wider SIMD ISA. At the same time, graphics processing units (GPUs) are gradually adding more general purpose programming features.

Two key software development challenges arise from these trends. First, how do we mitigate the increased software development complexity that comes with exposing parallelism to developers? Secondly, how do we provide portability across (increasing) core counts and SIMD ISA?

Researchers at Intel’s Microprocessor Technology Lab have developed a new programming model called Ct to address both of these challenges. Ct is a deterministic parallel programming model intended to leverage the best features of emerging general-purpose GPU (GPGPU) programming models while fully exploiting CPU flexibility. A key distinction of Ct is that it is a comprehensive data parallel programming model that gives programmers the flexibility to write code for multiple processor architectures. By contrast, most GPGPU programming models take are designed around the underlying constraints of the architecture for which code will be written.

Read the full Ct: Flexible Parallel Programming for Tera-scale Architectures White Paper.