Logic fault isolation (FI) processes are used to identify specific nodes for further analysis. With the rapidly increasing number of nodes in modern CMOS devices, automated tools leveraging design for testability (DFT) features are now used to do most of the FI.
Scan is a DFT solution that allows control and observability of internal states through scan cells that are dispersed throughout the design. It improves test coverage and is also effective for node localization during logic fault isolation. This is done through a diagnosis process that analyzes design, test pattern, and datalog information to establish a list of candidate nodes causing opens, shorts, or signal delays.
Large caches, such as L2 with sizes of 2 to 24 MB, cover a significant portion of the die area. Due to the relative ease of pinpointing the location of a specific cell, FI on caches is the main flow for defect analysis during manufacturing. Methods such as raster that can identify a single cell and low yield analysis (LYA) mode that can capture analog information of a specific cell are examples of cache DFT modes. When the measurements are compared to simulations, conclusions can be made as to the location of a defect.