This document provides the core, GBOX, and SBOX register information for the Intel® Xeon Phi™ coprocessor x100 product family. Core registers fetch and decode instructions from four hardware thread execution contexts. The Intel® Xeon Phi™ coprocessor memory controller (GBOX) accesses external memory devices (local physical memory on the coprocessor card) to read and write data. Each memory controller has two channels, which together can operate two 32-bit memory channels. A Gen2 PCI Express* client logic (SBOX) is the system interface to the host CPU or PCI Express switch which supports x8 and x16 configurations.