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Intel® Xeon® Processor L3406 Datasheet, Vol. 1

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Intel® Xeon® Processor L3406 Datasheet, Vol. 1

The Intel® Xeon® processor L3406 is the next generation of 64-bit, multi-core desktop processors built on 32-nanometer process technology. Based on the low-power/high-performance Intel microarchitecture, the processor is designed for a two-chip platform, as opposed to the traditional three-chip platforms (processor, (G)MCH, and ICH). The two-chip platform consists of a processor and Platform Controller Hub (PCH) and enables higher performance, easier validation, and improved x-y footprint. The Intel® 3400 Series Chipset components for servers and workstations are the PCH.

The Intel® Xeon® processor L3406 is intended for UP server and workstation platforms.

This document provides DC electrical specifications, signal integrity, differential signaling specifications, pinout and signal definitions, interface functional descriptions, and additional feature information pertinent to the implementation and operation of the processor on its respective platform.

Note: Throughout this document, the Intel Xeon processor L3406 may be referred to as “processor”.

Note: Some processor features are not available on all platforms. Refer to the processor. Specification update for details. Included in this family of processors is a memory controller die on the same package as the processor core die. This two-chip solution of a processor core die with a memory controller die is known as a Multi-Chip Package (MCP) processor. Figure 1-1 shows an example platform block diagram.

Note: Memory controller die is built on 45-nanometer process technology.

Read the full Intel® Xeon® Processor L3406 Datasheet, Vol. 1.