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Intel® Xeon® Processor E7 Family Uncore Performance Monitoring

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Intel® Xeon® Processor E7 Family Uncore Performance Monitoring

Figure 1-1 provides an Intel® Xeon® Processor E7 Family block diagram.

The processor uncore performance monitoring is supported by PMUs local to each of the C, S, B, M, R, U, and W-Boxes. Each of these boxes communicates with the U-Box which contains registers to control all uncore PMU activity (as outlined in Section 2.1, “Global Performance Monitoring Control Counter Over-flow”).

All processor uncore performance monitoring features can be accessed through RDMSR/WRMSR instructions executed at ring 0.

Since the uncore performance monitors represent socket-wide resources that are not context switched by the OS, it is highly recommended that only one piece of software (per-socket) attempt to program and extract information from the monitors. To keep things simple, it is also recommended that the monitoring software communicate with the OS such that it can be executed on coreId = 0, threadId = 0. Although recommended, this step is not necessary. Software may be notified of an overflowing uncore counter on any core.

Read the full Intel® Xeon® Processor E7 Family Uncore Performance Monitoring Programming Guide.