Intel® Xeon® Processor 3400 Series Datasheet, Vol. 2
This is Volume 2 of the datasheet for the Intel® Xeon® processor 3400 series.
The processor contains one or more PCI devices within a single physical component. The configuration registers for these devices are mapped as devices residing on the PCI Bus assigned for the processor socket.
This document describes these configuration space registers or device-specific control and status registers (CSRs) only. This document does NOT include Model Specific Registers (MSRs).
Note: Throughout this document, the Intel® Xeon® processor 3400 series may be referred to as “processor”.
Note: Throughout this document, the Intel® 3400 series Chipset Platform Controller Hub is also referred to as “PCH”.
Note: The term “SRV” refers to server platforms. The term “WS” refers to workstation platforms.
Platform Configuration Structure
The DMI physically connects the processor and the Intel Platform Controller Hub (PCH). From a configuration standpoint, the DMI is logically PCI Bus 0. A physical PCI Bus 0 does not exist. DMI and the internal devices in the processor Integrated I/O (IIO) and Intel PCH logically constitute PCI Bus 0 to configuration software. As a result, all devices internal to the processor and the Intel PCH appear to be on PCI Bus 0.
The system primary PCI expansion bus is physically attached to the Intel PCH and, from a configuration perspective, appears to be a hierarchical PCI bus behind a PCI-to-PCI bridge and, therefore, has a programmable PCI Bus number. The PCI Express* Graphics Attach appears to system software to be a real PCI bus behind a PCI-to-PCI bridge that is a device resident on PCI Bus 0.
Read the full Intel® Xeon® Processor 3400 Series Datasheet, Vol. 2.