We are sorry, This PDF is available in download format only

Microsoft Word - Celeron D DGA.doc

Intel Pentium 4 Processor in 478-pin Package Guide Addendum

This document describes the required changes to platforms utilizing the Intel® Pentium® 4 processor with 512-KB L2 cache on 0.13 micron process to support a migration to the Intel® Celeron® D processor in the 478-pin package. The information in this document should be used in conjunction with specifications presented in the latest version of the Intel® Celeron® D Processors 335, 330, 325, and 320 Datasheet and Intel® Pentium® 4 Processor with 512-KB L2 Cache on 0.13 Micron Process and Intel® Pentium® 4 Processor Extreme Edition Supporting Hyper-Threading Technology Datasheet.

This design guide addendum is provided as a supplement to the platform design guidelines from documents listed in Section 1.2. This document highlights changes to the platform design guidelines for the purpose of adding support for the Intel Celeron D Processor in the 478-pin package. All other design implementation details from the platform design guidelines are applicable for the Intel Celeron D processor in the 478-pin package support, given the limitations described in Section 2.

State of the Data

This document contains compatibility requirements between the Intel Celeron D processor in the 478-pin package and the Intel Pentium 4 processor with 512-KB L2 cache on 0.13 micron process with the 845 family of chipset based platforms.

The board-level electrical design changes (system bus routing recommendations, new signal definition, system bus termination recommendations, etc.) are the most up to date design details for the Intel Celeron D processor in the 478-pin package. This includes the pinout changes and their implementation for a “compatible platform” (see Section 1.3 for definition).

Read the full Intel® Pentium® 4 Processor in 478-pin Package Guide Addendum.

Intel Pentium 4 Processor in 478-pin Package Guide Addendum

This document describes the required changes to platforms utilizing the Intel® Pentium® 4 processor with 512-KB L2 cache on 0.13 micron process to support a migration to the Intel® Celeron® D processor in the 478-pin package. The information in this document should be used in conjunction with specifications presented in the latest version of the Intel® Celeron® D Processors 335, 330, 325, and 320 Datasheet and Intel® Pentium® 4 Processor with 512-KB L2 Cache on 0.13 Micron Process and Intel® Pentium® 4 Processor Extreme Edition Supporting Hyper-Threading Technology Datasheet.

This design guide addendum is provided as a supplement to the platform design guidelines from documents listed in Section 1.2. This document highlights changes to the platform design guidelines for the purpose of adding support for the Intel Celeron D Processor in the 478-pin package. All other design implementation details from the platform design guidelines are applicable for the Intel Celeron D processor in the 478-pin package support, given the limitations described in Section 2.

State of the Data

This document contains compatibility requirements between the Intel Celeron D processor in the 478-pin package and the Intel Pentium 4 processor with 512-KB L2 cache on 0.13 micron process with the 845 family of chipset based platforms.

The board-level electrical design changes (system bus routing recommendations, new signal definition, system bus termination recommendations, etc.) are the most up to date design details for the Intel Celeron D processor in the 478-pin package. This includes the pinout changes and their implementation for a “compatible platform” (see Section 1.3 for definition).

Read the full Intel® Pentium® 4 Processor in 478-pin Package Guide Addendum.

Related Videos