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Intel® Itanium® Processor Family Error Handling GuidePurposeThis Intel® Itanium® Processor Family Error Handling Guide describes error handling on Itanium®-based systems. It provides guidelines for firmware and operating systems to take advantage of the Itanium Advanced Machine Check Architecture. This document references the Processor Abstraction Layer (PAL) and System Abstraction Layer (SAL) specifications and shows how firmware, platform design, and the operating system cooperate to address corrected errors and machine check aborts.Target AudienceThis document is intended for Itanium architecture SAL developers, platform designers, and OS developers. Implementation-specific details of processors are not discussed in this document. The target audience is expected to be familiar with the PAL and SAL specifications.Related DocumentsThis document refers to the following publications:• Intel® Itanium® Architecture Software Developer’s Manual, available for download at http://developer.intel.com/design/itanium/manuals/iiasdmanual.htm• Intel® Itanium® Processor Family System Abstraction Layer Specification, downloadable at https://www-ssl.intel.com/content/www/us/en/processors/itanium/itanium-processor-9000-sequence.html• OS Machine Check Recovery on Itanium-Based Systems Application Note, available for download at http://developer.intel.com• Unified Extensible Firmware Interface Specification, available for download at http://www.uefi.org/home• DIG64 Corrected Platform Error Polling Interface Specification, available for download at http://www.dig64.orgRead the full Intel® Itanium® Processor Family Error Handling Guide.
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