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Intel Platform Innovation Framework for EFI System Management Mode Core Interface Specification (SMM CIS) v0.9

EFI System Management Mode Core Interface Spec (SMM CIS) v0.9

Overview

This specification defines the core code and services that are required for an implementation of the System Management Mode (SMM) phase of the Intel® Platform Innovation Framework for EFI (hereafter referred to as the “Framework”). This SMM Core Interface Specification (CIS) does the following:
• Describes the basic components of SMM
• Provides code definitions for services and functions that are architecturally required by the Intel® Platform Innovation Framework for EFI Architecture Specification
• Describes the interactions between SMM and other phases in the Framework
• Describes processor-specific details in SMM mode for IA-32 and Intel® Itanium® processors. See Organization of the SMM CIS for more information.

Rationale

Certain artifacts of the hardware and platform design require programmatic workarounds. This interface design aims to provide a clean mechanism for installing these modules. Possible candidates include the following:
• ACPI S3 reserve handler
• Enable/disable ACPI mode
• Power button support while not in ACPI mode
• Error logging for ECC/PERR/SERR in IA-32
• Protected flash writes on some IA-32 platforms
• Century rollover bug workaround

Organization of the SMM CIS

Read the full SMM core interface specification for the Intel® Platform Innovation Network for EFI.

EFI System Management Mode Core Interface Spec (SMM CIS) v0.9

Overview

This specification defines the core code and services that are required for an implementation of the System Management Mode (SMM) phase of the Intel® Platform Innovation Framework for EFI (hereafter referred to as the “Framework”). This SMM Core Interface Specification (CIS) does the following:
• Describes the basic components of SMM
• Provides code definitions for services and functions that are architecturally required by the Intel® Platform Innovation Framework for EFI Architecture Specification
• Describes the interactions between SMM and other phases in the Framework
• Describes processor-specific details in SMM mode for IA-32 and Intel® Itanium® processors. See Organization of the SMM CIS for more information.

Rationale

Certain artifacts of the hardware and platform design require programmatic workarounds. This interface design aims to provide a clean mechanism for installing these modules. Possible candidates include the following:
• ACPI S3 reserve handler
• Enable/disable ACPI mode
• Power button support while not in ACPI mode
• Error logging for ECC/PERR/SERR in IA-32
• Protected flash writes on some IA-32 platforms
• Century rollover bug workaround

Organization of the SMM CIS

Read the full SMM core interface specification for the Intel® Platform Innovation Network for EFI.

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