These manuals describe the architecture and programming environment of the Intel® 64 and IA-32 architectures.
Electronic versions of these documents allow you to quickly get to the information you need and print only the pages you want. The Intel® 64 and IA-32 architectures software developer's manuals are now available for download via a three volume set or an eight volume set. All content is identical in each set; see details below.
At present, downloadable PDFs of all volumes are at version 059. The downloadable PDF of the Intel® 64 and IA-32 architectures optimization reference manual is at version 033. Additional related specifications, application notes, and white papers are also available for download.
Note: If you would like to be notified of updates to the Intel® 64 and IA-32 architectures software developer's manuals, you may utilize a third-party service, such as http://www.changedetection.com/ to be notified of changes to this page (please reference 1 below).
Note: We are no longer offering the Intel® 64 and IA-32 architectures software developer’s manuals on CD-ROM. Hard copy versions of the manual are available for purchase via a print-on-demand fulfillment model through a third-party vendor, Lulu (please reference 1 and 2 below): http://www.lulu.com/spotlight/IntelSDM.
| Document | Description |
|---|---|
| Intel® 64 and IA-32 architectures software developer’s manual combined volumes: 1, 2A, 2B, 2C, 2D, 3A, 3B, 3C and 3D | This document contains the following: Volume 1: Describes the architecture and programming environment of processors supporting IA-32 and Intel® 64 architectures. Volume 2: Includes the full instruction set reference, A-Z, in one volume. Describes the format of the instruction and provides reference pages for instructions. Volume 3: Includes the full system programming guide, Parts 1, 2, and 3, in one volume. Describes the operating-system support environment of Intel® 64 and IA-32 architectures, including: memory management, protection, task management, interrupt and exception handling, multi-processor support, thermal and power management features, debugging, performance monitoring, system management mode, virtual machine extensions (VMX) instructions, Intel® Virtualization Technology (Intel® VT), and Intel® Software Guard Extensions (Intel® SGX). |
| Intel® 64 and IA-32 architectures software developer's manual documentation changes | Describes bug fixes made to the Intel® 64 and IA-32 architectures software developer's manual between versions. NOTE: This change document applies to all Intel® 64 and IA-32 architectures software developer’s manual sets (combined volume set, 3 volume set, and 8 volume set). |
| Document | Description |
|---|---|
| Intel® 64 and IA-32 architectures software developer's manual volume 1: Basic architecture | Describes the architecture and programming environment of processors supporting IA-32 and Intel® 64 architectures. |
| Intel® 64 and IA-32 architectures software developer's manual combined volumes 2A, 2B, 2C, and 2D: Instruction set reference, A-Z | This document contains the full instruction set reference, A-Z, in one volume. Describes the format of the instruction and provides reference pages for instructions. This document allows for easy navigation of the instruction set reference through functional cross-volume table of contents, references, and index. |
| Intel® 64 and IA-32 architectures software developer's manual combined volumes 3A, 3B, 3C, and 3D: System programming guide | This document contains the full system programming guide, parts 1, 2, 3, and 4, in one volume. Describes the operating-system support environment of Intel® 64 and IA-32 architectures, including: Memory management, protection, task management, interrupt and exception handling, multi-processor support, thermal and power management features, debugging, performance monitoring, system management mode, virtual machine extensions (VMX) instructions, Intel® Virtualization Technology (Intel® VT), and Intel® Software Guard Extensions (Intel® SGX). This document allows for easy navigation of the system programming guide through functional cross-volume table of contents, references, and index. |
| Document | Description |
|---|---|
| Intel® 64 and IA-32 architectures software developer's manual volume 1: Basic architecture | Describes the architecture and programming environment of processors supporting IA-32 and Intel® 64 architectures. |
| Intel® 64 and IA-32 architectures software developer's manual volume 2A: Instruction set reference, A-L | Describes the format of the instruction and provides reference pages for instructions (from A to L). This volume also contains the table of contents for volumes 2A, 2B, 2C and 2D. |
| Intel® 64 and IA-32 architectures software developer's manual volume 2B: Instruction set reference, M-U | Provides reference pages for instructions (from M to U). |
| Intel® 64 and IA-32 architectures software developer's manual volume 2C: Instruction set reference, V-Z |
Provides reference pages for instructions (from V to Z). |
| Intel® 64 and IA-32 architectures software developer's manual volume 2D: Instruction set reference | Includes the safer mode extensions reference. This volume also contains the appendices and index support for volumes 2A, 2B, 2C, and 2D. |
| Intel® 64 and IA-32 architectures software developer's manual volume 3A: System programming guide, part 1 | Describes the operating-system support environment of an IA-32 and Intel® 64 architectures, including: memory management, protection, task management, interrupt and exception handling, and multi-processor support. This volume also contains the table of contents for volumes 3A, 3B, and 3C. |
| Intel® 64 and IA-32 architectures software developer's manual volume 3B: System programming guide, part 2 | Continues the coverage on system programming subjects begun in volume 3A. Volume 3B covers thermal and power management features, debugging, and performance monitoring. |
| Intel® 64 and IA-32 architectures software developer's manual volume 3C: System programming guide, part 3 | Continues the coverage on system programming subjects begun in volume 3A and volume 3B. Volume 3C covers system management mode, virtual machine extensions (VMX) instructions, and Intel® Virtualization Technology (Intel® VT). |
| Intel® 64 and IA-32 architectures software developer's manual volume 3D: System programming guide, part 4 | Volume 3D covers system programming with Intel® Software Guard Extensions (Intel® SGX). This volume also contains the appendices and indexing support for volumes 3A, 3B, 3C, and 3D. |
| Document | Description |
|---|---|
| Intel® 64 and IA-32 architectures optimization reference manual | Intel® 64 and IA-32 architectures optimization reference manual provides information on Intel® Core™ processors, NetBurst microarchitecture, and other recent Intel® microarchitectures. It describes code optimization techniques to enable you to tune your application for highly optimized results when run on Intel® Atom™, Intel® Core™ i7, Intel® Core™, Intel® Core™2 Duo, Intel® Core™ Duo, Intel® Xeon®, Intel® Pentium® 4, and Intel® Pentium® M processors. |
| Document | Description |
|---|---|
| Timestamp-Counter Scaling for Virtualization | This paper describes an Intel® Virtualization Technology (Intel® VT) enhancement for future Intel® processors. This feature, referred to as timestamp-counter scaling (TSC scaling), further extends the capability of virtual-machine monitor (VMM) software that employs the TSC-offsetting mechanism by allowing that software finer control over the value of the timestamp counter (TSC) read during guest virtual machine (VM) execution. |
| Intel® 64 architecture x2APIC specification | Extensions to the xAPIC architecture are intended primarily to increase processor addressability. The x2APIC architecture provides backward compatibility to the xAPIC architecture and forward extendability for future Intel platform innovations. |
| Intel® 64 and IA-32 architectures application note TLBs, paging-structure caches, and their invalidation | The information contained in this application note is now part of Intel® 64 and IA-32 architectures software developer's manual volumes 3A and 3B. |
| Intel® Advanced Encryption Standard New Instructions (Intel® AES-NI) set white paper | This paper gives an overview of the AES algorithm and the Intel® AES-NI. It provides guidelines and demonstrations for using these instructions to write secure and high performance AES implementations. |
| Intel® architecture instruction set extensions programming reference | This document covers new instructions slated for future Intel® processors. |
| Intel® carry-less multiplication instruction and its usage for computing the GCM mode white paper | This paper provides information on the instruction, and its usage for computing the Galois Hash. It also provides code examples for the usage of PCLMULQDQ, together with the Intel® AES New Instructions (Intel® AES-NI) for efficient implementation of AES in Galois Counter Mode (AES-GCM). |
| Intel® 64 architecture memory ordering white paper | This document has been merged into Volume 3A of Intel® 64 and IA-32 architectures software developer’s manual. |
| MCA enhancements in future Intel® Xeon® processors | This white paper describes enhanced MCA logs and the reporting mechanism of IOMCA in future Intel® Xeon processors. |
| Performance monitoring unit sharing guide | This paper provides a set of guidelines between multiple software agents sharing the PMU hardware on Intel® processors. |
| Intel® Virtualization Technology FlexMigration (Intel® VT FlexMigration) application note | This application note discusses virtualization capabilities in Intel® processors that support Intel® VT FlexMigration usages. |
| Intel® Virtualization Technology for Directed I/O architecture specification |
This document describes the Intel® Virtualization Technology for Directed I/O. |
| Page Modification Logging for Virtual Machine Monitor white paper | This paper describes an Intel® Virtualization Technology (Intel® VT) enhancement for future Intel® processors.
|
| Secure Access of Performance Monitoring Unit by User Space Profilers | This paper proposes a software mechanism targeting performance profilers which would run at user space privilege to access performance monitoring hardware. The latter requires privileged access in kernel mode, in a secure manner without causing unintended interference to the software stack. |