The objective of the Intel validation program is to verify SDRAM compliance to Intel specifications for and performance of supported DDR memory modules in Intel reference systems. The results of validation procedures provide a guideline for memory compatibility with Intel® Chipsets.
This validation, performed by approved test labs on small samples of components and modules, is intended to demonstrate supplier design and manufacturing capability.
The validation process uses standardized procedures and methodologies documented in the Intel validation procedure for DDR, DDR2,DDR3 and DDR3L. This documented procedure is not intended to replace the normal product qualification process.
Latest validation updates
- Intel® Core™ i7 and Core™ i5 Processors (Ivy Bridge) - SoDIMM tested at 1333/1600 MT/s – 1.35V
- Intel® Core™ i7 and Core™ i5 Processors (Ivy Bridge) - SoDIMM tested at 1600 MT/s – 1.5V
- Intel® Xeon® E3 Processor 1200 v2 Series (Ivy Bridge) - UDIMM ECC tested at 1600 MT/s – 1.5V
- Intel® Core™ i7 and Core™ i5 Processors (Ivy Bridge) - UDIMM Non-ECC tested at 1600 MT/s – 1.5V
Intel® Xeon® Processor E5-2600 Series (SandyBridge-EP)
Validation results
| DDR3 R/LRDIMM |
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|---|---|---|
| Future Intel® Xeon® Processor E5 family (formerly codenamed SandyBridge-EP) |
LRDIMM tested at 1066 and 1333 MT/s – 1.35V and 1.5V | |
| RDIMM tested at all supported speeds – 1.35V and 1.5V | ||
| Intel® Xeon® Processor E7-8800 Series (Westmere-EX) | RDIMM tested at 800/978/1066 MT/s – 1.35V and 1.5V | |
| Intel® Xeon® Processor 7500 Series (Nehalem-EX) | RDIMM tested at 800/973/1066 MT/s – 1.5V | |
| Intel® Xeon® Processor 5600 Series (Westmere-EP) |
RDIMM tested at 1066/1333 MT/s 1.5V | |
| RDIMM tested at 1066/1333 MT/s – 1.35V | ||
| DDR3 ECC UDIMM | ||
| Future Intel® Xeon® Processor E5 family (formerly codenamed SandyBridge-EP) | UDIMM-ECC tested at 1600 MT/s – 1.5V | |
| Intel® Xeon® Processor 5600 Series (Westmere-EP) |
UDIMM ECC tested at 800/1066/1333 MT/s – 1.5V | |
| UDIMM ECC tested at 1333 MT/s – 1.35V | ||
| Intel® Xeon® E3 Processor 1200 Series (Bromolow) | UDIMM ECC tested at 1333 MT/s – 1.5V | |
| Intel® Xeon® E3 Processor 1200 v2 Series (Ivy Bridge) | UDIMM ECC tested at 1600 MT/s – 1.5V | |
| DDR3 Non-ECC UDIMM |
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| Intel® Core™ i7 and Core™ i5 Processors (Sandy Bridge) | UDIMM Non-ECC tested at 1333 MT/s – 1.5V | |
| Intel® Core™ i7 Processor (Sandy Bridge-E) | UDIMM Non-ECC tested at 1600 MT/s – 1.5V | |
| Intel® Core™ i7 and Core™ i5 Processors (Ivy Bridge) |
UDIMM Non-ECC tested at 1600 MT/s – 1.5V | |
| DDR3 SODIMM |
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| Intel® Core™ i7 and Core™ i5 Processors (Sandy Bridge) | SoDIMM tested at 1333/1600 MT/s – 1.5V | |
| Intel® Core™ i7 and Core™ i5 Processors (Ivy Bridge) |
SoDIMM tested at 1333/1600 MT/s – 1.35V | |
| Intel® Core™ i7 and Core™ i5 Processors (Ivy Bridge) |
SoDIMM tested at 1600 MT/s – 1.5V | |
| Validation procedures |
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| Overview |
The objective of the validation process is to enable a smooth and quick integration of DDR2-based systems. | |
| DIMM validation process |
The objective of the Intel validation program for DDR, DDR2, and DDR3 is to verify DDR SDRAM compliance to the Intel specifications for DDR/DDR2/DDR3 and performance of DDR/DDR2/DDR3 DIMM modules in Intel reference systems, so as to provide a guideline for memory compatibility with Intel chipsets. | |
| Related links |
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