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DDR Signal Integrity and Layout

Vira Ragavassamy presents practical tips and steps for signal integrity simulation on a DDR interface, including new memory controller features.

Embedded Intel® Architecture Board Layout Checking Guide

Checking guide presents best practices for board layout review, including review of power delivery, system clocks, and interfaces. (v.1, Dec. 2009)

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Signal Integrity Introduction

Vira Ragavassamy presents a signal integrity introduction and detailed steps for signal integrity simulation on Intel® architecture. (Dec. 2008)

User Interface for SATA Motherboard Signal Quality Test Setup

White Paper: Introduces alternative AHCI register and user interface to perform setup for the SATA motherboard signal quality test. (v.1, Dec. 2009)

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