Specification Update, 2009: Intel® 5400 Express Chipset memory controller hub (MCH), clarifications, changes, and documentation errata.
Specification updates for the Intel® 5400 Express Chipset Memory Controller Hub (MCH), including device and documentation errata, specification clarification, and changes.
Application Note 726: Intel® E7500 Chipset MCH Intel® x4 Single Device Data Correction implementation and validation.
Covers the implementation and validation of the Intel® E7500 Chipset MCHs support of Intel® x4 Single Device Data Correction, which provides Single x4 Error Correction-Double x4 Error Detection.
Discusses mixing x4 DIMMs with x8DIMMs on a platform that contains the A2 stepping of the Intel® E7500 MCH.
This application note discusses mixing x4 DIMMs with x8DIMMs on a platform that contains the A2 stepping of the Intel® E7500 MCH.
Contains MCH signals, registers, DC electrical characteristics, ballout, package dimensions, and component testability for Intel E7505.
This document describes the MCH signals, registers, DC electrical characteristics, ballout, package dimensions, and component testability. The major functional blocks of the MCH are described.
Datasheet: Intel® E8500 chipset External Memory Bridge (XMB).
This document, the Intel® E8500 Chipset external Memory Bridge (XMB) Datasheet, describes the features, modes and registers supported by the XMB component only.