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Pattern Matching Performance with HyperScan* Software: Brief

Solution Brief: Discusses pattern matching performance optimization of Sensory Networks HyperScan* software with Intel® Xeon® processors.

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Data Plane Packet Processing Embedded Intel® Architecture: Paper

White Paper: Discusses techniques for overcoming challenges to achieve high-performance data plane packet processing on embedded Intel® architecture.

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Open Standards for Open Source Software

Support open standards and improve NFV and SDN with Intel® Open Network Platform reference designs and Open Software Community solutions.

Optimized AES Galois-Counter Mode Software

Software: Various versions of AES Galois-Counter Mode assembly code optimized for different Intel® Architecture Processors.

Intel® Multi-Buffer Crypto for IPSec: Install Package

Install Package: Download the Intel® Multi-Buffer Crypto for IPSec, including a comprehensive library of functions for different Intel® architectures.

Optimized ISCSI CRC Using CRC32 Instruction Software

Software: Optimized code to compute the Internet Small Computer System Interface cyclic redundancy check using CRC32 and PCLMULQDQ instructions.

Software: Fast CRC16 Code for T10 DIF

Software: Use this optimized function to compute a 16-bit cyclic redundancy check as defined in the T10 DIF standard using PCLMULQDQ instruction.

Intel® Data Plane Development Kit Optimizes Packet Processing

Presentation: The Intel® Data Plane Development Kit enables multi-workloads on single architecture optimized for packet processing. (v.001, Dec. 2012)

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AES CBC Encrypt/Decrypt for Sandy Bridge

Source Code: AES CBC Encrypt Multibuffer / Decrypt Single Buffer optimized for Sandy Bridge

Intel® Data Plane Development Kit: API Reference

API Reference: Depreciated list, data structure documentation, and file documentation for the Intel® Data Plane Development Kit. (v.6, Jan. 2014)

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