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Intel® Scalable System Architecture Specification

This specification for high performance computing systems enables a high degree of commonality and interoperability between systems.

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Intel® Scalable System Framework Reference Design

This Intel® SSF Reference Design includes Intel® Xeon® processor E5-2600 v4 product family and Intel® OPA, and uses the OpenHPC software stack.

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Jefferson Lab Improves Application Performance Case Study

Jefferson Lab improves scientific application performance for faster results with Intel® Xeon Phi™ coprocessor-based Seneca servers and Linux* OS.

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EFI Cache Subclass Specification v0.9

Defines core code for an implementation of the cache data hub subclass of the Intel® Platform Innovation Framework for EFI.

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EFI CPU I/O Protocol Specification v0.9

Covers core code and services required for an implementation of the CPU I/O Protocol of the Intel® Platform Innovation Framework for EFI.

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EFI Human Interface Infrastructure Specification v0.91

Defines core code for implementation of Human Interface Infrastructure of the Intel® Platform Innovation Framework for EFI.

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EFI Human Interface Infrastructure Specification v0.92

Defines core code for an implementation of the Human Interface Infrastructure of the Intel® Platform Innovation Framework for EFI.

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EFI System Management Mode Core Interface Spec (SMM CIS) v0.9

Defines the core code and services required for implementation of the System Management Mode of the Intel® Platform Innovation Framework for EFI.

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EFI Status Codes Specification v0.92

Updated: Defines the basic components, status code classes, and status code architecture required for Intel® Platform Innovation Framework for EFI.

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EFI Human Interface Infrastructure Specification v0.9

This document describes the mechanisms by which the Intel® Platform Innovation Framework for EFI (the “Framework”) manages user input.

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