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Jefferson Lab Improves Application Performance Case Study

Jefferson Lab improves scientific application performance for faster results with Intel® Xeon Phi™ coprocessor-based Seneca servers and Linux* OS.

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EFI System Management Mode Core Interface Spec (SMM CIS) v0.9

Defines the core code and services required for implementation of the System Management Mode of the Intel® Platform Innovation Framework for EFI.

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UEFI Boot Time Optimization: Intel, Microsoft, and Insyde

Overview of boot time, performance improvements, sample results, demo, why fast POST for Windows 7, other considerations for Windows 8

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EFI Cache Subclass Specification v0.9

Defines core code for an implementation of the cache data hub subclass of the Intel® Platform Innovation Framework for EFI.

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EFI SMBus PPI Specification v0.9

Defines the core code, services, and design required in the system management bus PEIM to PEIM for the Intel® Platform Innovation Framework for EFI.

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EFI Human Interface Infrastructure Specification v0.92

Defines core code for an implementation of the Human Interface Infrastructure of the Intel® Platform Innovation Framework for EFI.

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EFI Memory Subclass Specification v0.9

Specification defines required core code and services for the memory data hub subclass of the Intel® Platform Innovation Framework for EFI.

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EFI Miscellaneous Subclass Specification v0.9

Defines core code for implementation of the miscellaneous data hub subclass of the Intel® Platform Innovation Framework for EFI.

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EFI Hand-Off Block (HOB) Specification v0.9

Hand-Off Block Specification for the Intel® Platform Innovation Framework for EFI defines core code required for implementation.

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EFI Recovery Specification v0.9

Defines the recovery architecture, core code, and services required for the implementation of the in the Intel® Platform Innovation Framework for EFI.

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