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PCI Express* Architecture

The Intel developer network for PCI Express* architecture is a developer community offering access to resources and peers.

Wireless Host Controller Interface Specification

The Wireless Host Controller Interface describes the register-level interface for a Host Controller for Wireless (USB) Revision 1.0.

USB – Universal Serial Bus 3.0 and 2.0 Specifications

Technical details to understand USB 3.0 and 2.0 spec requirements, design compatible products, download developer-related PDFs, and more.

Intel® USB FAQ

Intel® Universal Serial Bus (USB) Frequently Asked Questions about SuperSpeed USB 3.0, High-Speed USB 2.0, USB 2.0, & USB On-the-Go.

PCI Express* Architecture

PCI Express* Architecture is a standards-based serial data, multi-lane interconnect for high-performance, scalable interconnects.

USB EHCI Compliance Test Program

USB EHCI compliance test information for evaluating USB 2.0 host controller conformance and function, suggested components, download link, and more.

Thunderbolt™ for Developers

Transforming I/O device interconnectivity and transfer performance, Thunderbolt™ technology enables flexible, innovative system design configurations.

PCI Express* Architecture

PCI Express* Architecture is a standards-based serial data, multi-lane interconnect for high-performance, scalable interconnects.

Serial ATA AHCI: Specification, Rev. 1.2

Defines functional behavior and Advanced Host Controller Interface software for moving data between system memory and serial ATA devices.

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Serial ATA AHCI: Device Sleep Technical Proposal, Rev. 1.3.1

Programming register definitions, a method to detect support for direct software control, and a method for HW to autonomously enter and exit DevSleep.

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