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PCI Express* Compliance Load Board Demo

PCI Express* Compliance Load Board demo covers tools, oscilloscope, platform, waveform analysis, SigTest software, and reports. (v.001, Mar. 2010)

Reduce Interrupt Latency in Embedded Systems

White Paper: MSI remove limitations associated with Intel® architecture, reduce interrupt latency and overhead, improving performance. (Jan. 2009)

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Intel® Atom™ Processor C2000 Product Family Specification Update

Update to the Intel® 64 and IA-32 Architectures Software Developer’s Manual, with device and documentation errata, spec clarifications, and changes.

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Connector Model Quality Assessment Methodology

White Paper: Defines model types to describe connector behavior, evaluation model for measuring accuracy, and quality levels for electrical models.

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How to Implement a 64B PCIe* Burst Transfer on Intel® Architecture

White Paper: How to implement a 64B PCIe* burst transfer on Intel® architecture using cache attributes and fence instructions. (v.001, Feb. 2013)

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Configure PCI-Express* Lanes for Simultaneous Applications

Configurations for PCI-Express* lanes on Intel® Core™ i7 processors, providing an interface for multiple simultaneous applications. (v.001, Dec. 2010)

PCI Express* Motherboard Signal Quality Testing: Guide

User Guide: PCI Express* Signal Quality Test Procedure gauges Intel® motherboard design to verify compliance to base specs. (v.1.01, Mar. 2007)

PCI Express* 12V Power Delivery Testing: Guide

User Guide: PCI Express* Power Delivery Test procedure verifies voltage and current delivery of motherboard PCI Express slots. (v.1, December 7, 2008)

Minimize the Impact of Virtualization

Learn how to minimize the impact of virtualization on interrupt latency and Intel® AVX while improving the performance of both. (v.001, Aug. 2011)

Channel Tools: Files

Contains introduction & user guides for channel tools: Intel® Channel Checker, Channel Quality Comparison, and Channel Check Tool. (v.2.0, July 2013)