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Interfacing I²C* Devices to SMBus Controller

White Paper: Determine how to interface I²C* devices and Intel® I/O Controller Hub SMBus controller with analysis guidelines. (Jan. 2009)

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Intel® 7 Series and Intel® C216 Chipsets: SPI Programming Guide

SPI Programming Guide: Requirements, tools, and procedures for programming SPI flash on Intel® 7 Series and Intel® C216 chipsets. (v.0.9, Sept. 2011)

EFI System Management Mode Core Interface Spec (SMM CIS) v0.9

Defines the core code and services required for implementation of the System Management Mode of the Intel® Platform Innovation Framework for EFI.

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UEFI Boot Time Optimization: Intel, Microsoft, and Insyde

Overview of boot time, performance improvements, sample results, demo, why fast POST for Windows 7, other considerations for Windows 8

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EFI Cache Subclass Specification v0.9

Defines core code for an implementation of the cache data hub subclass of the Intel® Platform Innovation Framework for EFI.

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EFI SMBus PPI Specification v0.9

Defines the core code, services, and design required in the system management bus PEIM to PEIM for the Intel® Platform Innovation Framework for EFI.

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EFI Human Interface Infrastructure Specification v0.92

Defines core code for an implementation of the Human Interface Infrastructure of the Intel® Platform Innovation Framework for EFI.

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EFI Memory Subclass Specification v0.9

Specification defines required core code and services for the memory data hub subclass of the Intel® Platform Innovation Framework for EFI.

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EFI Miscellaneous Subclass Specification v0.9

Defines core code for implementation of the miscellaneous data hub subclass of the Intel® Platform Innovation Framework for EFI.

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EFI Hand-Off Block (HOB) Specification v0.9

Hand-Off Block Specification for the Intel® Platform Innovation Framework for EFI defines core code required for implementation.

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