White Paper: Demos IPSec performance capabilities in Linux* using Intel® AES New Instructions and Galois Counter Mode* algorithm combination.
White Paper: Describes the performance characteristics of fast prototype implementations of DEFLATE compression on Intel® processors which addresses the burdens on servers to process huge amounts of data. (v.1, Nov. 2011)
White Paper: Proposes extensions to cryptographic hash algorithms that add support for parallel processing of a single message, describes overall design, and presents performance summary. (v.001, July 2012)
White Paper: Demonstrates how an alternative approach to integrating cipher algorithms optimized for Intel® AES New Instructions (Intel® AES-NI) can deliver up to 6x performance gain in the Linux* storage subsystem (v.1, Feb. 2013).
White Paper: Covers critical operations required in large integer arithmetic for efficient implementation using new instructions on Intel® Architecture Processors. (v.001, Jan. 2013)
White Paper: Describes a family of highly optimized implementations of the SHA512 cryptographic hash algorithm, which provide industry leading performance on a range of Intel® processors. (v.1, Nov. 2012)
White Paper: Describes the performance characteristics of an optimized implementation of storage encryption defined in the IEEE P1619 standard, benefiting from the AES-NI instructions on Intel® architecture. (v.1, Aug. 2010)
White Paper: Describes highly-optimized Fast SHA-256 cryptographic hash algorithm implementations for Intel® processors. (v.001, May 2012)
White Paper: Describes a family of highly-optimized implementations of the Fast SHA-256 cryptographic hash algorithm providing industry leading performance on a range of Intel® processors. (v.001, May 2012)