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Cryptographic Performance on 2nd Gen Intel® Core™ Processors

Paper: Cryptographic application performance increases on 2nd generation Intel® Core™ processors over Intel® microarchitecture code named Westmere.

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Optimized Galois-Counter-Mode Implementation

White Paper: Optimized Galois-Counter-Mode execution combines stitching with polynomial multiplication, increasing performance on Intel® processors.

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Low Voltage Processor Options: Platform Brief, Mandarin

Mandarin, Platform Brief: With low voltage options, the Intel® Xeon® processor 5100 series provides efficient balanced power. (v.006, June 2009)

High Performance DEFLATE Decompression on Intel® Architecture

White Paper: Performance characteristics of an optimized implementation of DEFLATE decompression on Intel® processors. (v.001, Nov. 2010)

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High-Performance Storage Encryption on Intel® Architecture

White Paper: Describes the performance benefits of optimizing storage encryption on Intel® architecture. (v.1, Aug. 2010)

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Fast SHA512 Implementations on Intel® Architecture: White Paper

White Paper: Describes family of highly optimized implementations of the SHA512 cryptographic hash algorithm on Intel® processors (v.001, Nov. 2012).

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New Instructions Support Large Integer Arithmetic

White Paper: Describes critical operations required in large integer arithmetic and efficient implementations of new instructions. (v.001, Aug. 2012)

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Large Integer Squaring on Intel® Architecture Processors

White Paper: Critical operations in large integer arithmetic using new instructions on Intel® processors for fast implementation. (v.001, Jan. 2013)

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Novel Hashing Method Suitable for Lookup Functions: Paper

White Paper: Describes a hashing method suitable for lookup functions and how to compute a high-quality 64-bit hash digest on Intel® processors.

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Intel® AES New Instructions (Intel® AES-NI)

Intel® AES-NI is a new encryption instruction set, improving on the previous algorithm and accelerating data encryption.