Paper: composite high-K gate in the QWFET silicon substrate integration for thin electrical oxide, low gate leakage, and carrier confinement.
Paper covers integration of an advanced composite high-K gate stack in the QWFET silicon substrate, enabling thin electrical oxide, low gate leakage, effective carrier confinement, and high carrier velocity in the QW channel.
Discusses low gate-leakage silicon and non-silicon transistor nanotechnology using high-κ gate dielectrics and metal gate electrodes.
Paper discusses high-performance and low gate-leakage silicon and non-silicon transistor nanotechnology research using high-κ gate dielectrics and metal gate electrodes.
Paper examines and evaluates logic performance of Schottky-gate QWFETs against that of advanced Strained Si MOSFETs in low power voltages.
Paper examines and evaluates logic performance of Schottky-gate QWFETs against that of advanced Strained Si MOSFETs in low power applications.
Intel introduces new 22nm technology.
Intel introduces a fundamentally different technology for future microprocessor families: 3-D transistors manufactured at 22nm. These new transistors enable Intel to continue to relentlessly pursue Moore's Law.
Backgrounder: Intel's 22nm innovation ushers in new semiconductor technology and ensures the continuation of Moore's Law.
For the first time in history, silicon transistors are entering the third dimension. Intel is introducing the tri-gate transistor, in which the transistor channel is raised into the 3rd dimension.
Mark Bohr explains how Intel 3-D transistors manufactured at 22nm ensure the pace of technology advancement for years to come.
Intel's 3-D Tri-Gate transistor, and the ability to manufacture it in high volume, mark a dramatic change in the fundamental structure of the computer chip. Learn more about the history of transistors.