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Guide: Describes the real-time instruction trace programming interface with examples of common usage models, operational considerations, and more.
Guide: Describes the programming interface of the real-time instruction trace with examples of common usage models, operational considerations for sleep states and security initializations, background, and related processor mechanisms.
Mark Bohr explains how Intel 3-D transistors manufactured at 22nm ensure the pace of technology advancement for years to come.
Intel's 3-D Tri-Gate transistor, and the ability to manufacture it in high volume, mark a dramatic change in the fundamental structure of the computer chip. Learn more about the history of transistors.Full View >
Intel’s Ishu Verma discusses Android* optimization on Intel® architecture-based platforms, including Android* SDK and NDK toolsets. (v.001, Oct. 2011)
Intel Platform Application Engineer Ishu Verma discusses Android* optimization on Intel® architecture-based platforms, including the Android* SDK and NDK toolsets as well as the benefits and drawbacks of using NDK. (v.001, Oct. 2011)Full View >
White Paper: Provides necessary steps and sample code to access Real Time Clock registers and NMI Enable Bit in I/O addresses 0x70-0x77. (Jan. 2009)
White Paper: Explains how to access the I/O addresses 0x70 through 0x77 for the Real Time Clock registers and the NMI Enable Bit with the necessary steps and sample code needed by BIOS and OS software to enable read and write. (Jan. 2009)
App Note: Covers home health gateway design challenges, starting with off-the-shelf Avalue Technology platform to decrease required design time.
Product Datasheet: Arch Rock PhyNet Server* manages and aggregates interconnected IP-based wireless sensor networks using a common web services architecture, featuring an intuitive web interface for convenient administration.
Detailed walk-through of how to set up Intel® Node Manager includes installing the system in the data center and configuration of energy monitoring.
Detailed walk-through shows how to set up a server with the Intel® Node Manager feature, includes unboxing the system, mounting into the data center, and configuration of power and thermal monitoring to manage system energy use.Full View >
White Paper: How to implement a 64B PCIe* burst transfer on Intel® architecture using cache attributes and fence instructions. (v.001, Feb. 2013)
White Paper: How to implement a 64B PCIe* burst transfer on Intel® architecture through the CPU core bus interface unit to a memory region reserved for a PCIe* device using cache attributes and fence instructions. (v.001, Feb. 2013)