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Packet Processing on Intel® Architecture with Data Plane Development Kit

Explains how packet processing on Intel® architecture and Data Plane Development Kit improve standard high-volume server performance.

Scaling Deep Packet Inspection with Hyperscan

Deep packet inspection on Wind River Open Virtualization* and Hyperscan demos improved security against threats to virtualized networks at RSA 2014.

Enhance Content Inspection with Hyperscan

Intel’s Chris Clark shows how Hyperscan software enhances content inspection by efficient matching of large data sets and patterns at RSA 2014.

libcrypto* Sample Patch for Intel® QuickAssist Technology

Libcrypto* sample patch for Intel® QuickAssist Technology and notes that discuss the features, limitations and installation. (v.0.4.9-009, Aug. 2015)

libcrypto* (OpenSSL*) Sample Patch, Intel® QuickAssist Technology

This is a release of libcrypto* (OpenSSL*) sample patch for Intel® QuickAssist Technology, available as doc. number 477629. (v.0.4.10-003, Aug. 2015)

Intel® Xeon® Processor E5-2400 Product Family: Thermal Guide

Thermal/mechanical, and heatsink design solutions for server and workstation processors in the Intel® Xeon® processor E5-2400 product family platform.

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Fast Cryptographic Computation Via Function Stitching

White Paper: Pair function stitching together in fine-grains to enable more cryptographic computation and performance gains on Intel® processors.

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Haswell U/Y Processor-based Platform: Design Guide

Guide: Provides Haswell U/Y platform design recommendations, including for Windows* 8, instrumentation, PCB, signal, and more. (v.2.5, Sep. 2014)

How to Implement a 64B PCIe* Burst Transfer on Intel® Architecture

White Paper: How to implement a 64B PCIe* burst transfer on Intel® architecture using cache attributes and fence instructions. (v.001, Feb. 2013)

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Low Power System Design with Memory Down

White Paper: Design a low power, scalable embedded system with memory down on the PCB instead of traditional memory connectors. (v.001, Aug. 2009)

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