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EFI Cache Subclass Specification v0.9

Defines core code for an implementation of the cache data hub subclass of the Intel® Platform Innovation Framework for EFI.

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EFI CPU I/O Protocol Specification v0.9

Covers core code and services required for an implementation of the CPU I/O Protocol of the Intel® Platform Innovation Framework for EFI.

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EFI System Management Mode Core Interface Spec (SMM CIS) v0.9

Defines the core code and services required for implementation of the System Management Mode of the Intel® Platform Innovation Framework for EFI.

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EFI Human Interface Infrastructure Specification v0.92

Defines core code for an implementation of the Human Interface Infrastructure of the Intel® Platform Innovation Framework for EFI.

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Jefferson Lab Improves Application Performance Case Study

Jefferson Lab improves scientific application performance for faster results with Intel® Xeon Phi™ coprocessor-based Seneca servers and Linux* OS.

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Platform Innovation Framework: UEFI Architecture Spec v0.9

Describes the architecture of the Intel® Platform Innovation Framework for EFI.

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Intel® Itanium® Processor 9500 Series: Reference Manual

Software development and optimization guide for the Intel® Itanium® processor 9500 series with microarchitectural description and performance info.

Enhanced MCA Logging in Future Intel® Xeon® Processors

White Paper: Provides usage models, software flows, and reporting mechanisms for enhanced MCA logging and I/O MCA in future Intel® Xeon® processors.

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EFI Human Interface Infrastructure Specification v0.9

This document describes the mechanisms by which the Intel® Platform Innovation Framework for EFI (the “Framework”) manages user input.

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EFI Pre-EFI Initialization Core Interface Specification v0.9

Defines the required core code and services for the Pre-EFI Initialization (PEI) phase of the Intel® Platform Innovation Framework for EFI.

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