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EFI Cache Subclass Specification v0.9

Defines core code for an implementation of the cache data hub subclass of the Intel® Platform Innovation Framework for EFI.

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EFI CPU I/O Protocol Specification v0.9

Covers core code and services required for an implementation of the CPU I/O Protocol of the Intel® Platform Innovation Framework for EFI.

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EFI System Management Mode Core Interface Spec (SMM CIS) v0.9

Defines the core code and services required for implementation of the System Management Mode of the Intel® Platform Innovation Framework for EFI.

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EFI Human Interface Infrastructure Specification v0.92

Defines core code for an implementation of the Human Interface Infrastructure of the Intel® Platform Innovation Framework for EFI.

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Intel® 7510/7512 Scalable Memory Buffer: Spec Update

Spec Update: Device and documentation errata, specification clarifications, and changes for the Intel® 7510/7512 Scalable Memory Buffer.

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Intel® Itanium® Processor: Specification Update

Intel® Itanium® processor provides device and documentation errata, specification clarifications, and changes.

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Intel® E8870 Chipset

Intel® E8870 Chipset allows for multi-node configurations of up to eight Intel® Itanium® processors, featuring the E8870SP component.

Intel® Itanium® Processor Technical Resources

Technical Resources list for Intel® Itanium® Processor includes applications notes, datasheets, packing information, product briefs, and more.

Tape Carrier Package: Databook, Chapter 12

Packaging Databook, Ch 12: Profile of the Tape Carrier Package and its uses in areas that require lightweight small footprint integrated circuits.

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Shipping and Transport Media: Packaging Databook, Ch. 10

Packaging Databook, Ch. 10: product and transport media, environmental programs, tape and reel, protective bands, and shipping formats.

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