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Data Plane Packet Processing Embedded Intel® Architecture: Paper

White Paper: Discusses techniques for overcoming challenges to achieve high-performance data plane packet processing on embedded Intel® architecture.

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AES CBC Encrypt/Decrypt for Sandy Bridge

Source Code: AES CBC Encrypt Multibuffer / Decrypt Single Buffer optimized for Sandy Bridge

Models for Packet Processing on Multi-Core Systems

White Paper: Compares models for packet processing on multi-core Intel® architecture systems explaining benefits, problems, and solutions.(Dec. 2008)

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Enhancing Data Plane Performance on Crystal Forest Platform

Learn how to run the Intel® Data Plane Development Kit in a Simics environment using the Crystal Forest platform to boost data plane performance.

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Intel® Embedded Technology: Intelligent Digital Signage

Learn how intelligent digital signage solutions enhance shopper experience with anonymous video analytics, interactive touch screens, and more.

Wind River Intelligent Network Platform* Presentation

Presentation: Trends, implications, and use case solutions based on the Wind River Intelligent Network Platform*. (v.1, Mar. 2014)

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Calsoft Service Offerings for Intel® Data Plane Development Kit

Presentation: Calsoft Labs describes service offerings for Intel® Data Plane Development Kit evaluation, implementation, deployment. (v.1, Jan. 2014)

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6WIND Support for Intel® Data Plane Development Kit Presentation

6WIND support for Intel® Data Plane Development Kit includes a stand-alone library and an integrated packet processing solution. (v.1, Jan. 2012)

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Workload Consolidation in Communications Infrastructure

Intel® Virtualization Technology enables workload consolidation on a single architecture, simplifying network complexity and management.

Radio Network Layer Data Plane Processing: Paper

White Paper: Describes how embedded Intel® architecture implements the workload associated with a Radio Network Layer Data Plane pipeline.

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